View MM908E622_2780887.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MM908E622 rev 1.0, 09/2005 freescale semiconductor technical data this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2005. all rights reserved. integrated quad half-bridge, triple high-side and ec glass driver with embedded mcu and lin for high end mirror the 908e622 is an integrated single-package solution that includes a high-performance hc08 microcontroller with a smartmos tm analog control ic. the hc08 includes flash memory, a timer, enhanced serial communications interface (esci), an analog-to-digital converter (adc), serial peripheral interface (spi) (only internal), and an internal clock generator module. the analog control die provides four half-bridg e and three high-side outputs with diagnostic functions, an ec glass driver circuit, a hall-effect sensor input, analog inputs, voltage regulator, window watchdog, and local interconnect network (lin) physical layer. the single-package solution, together with lin, provides optimal application performance adjustment s and space-saving pcb design. it is well suited for the control of automotive high-end mirrors. features ? high-performance m68hc908ey16 core ? 16 k bytes of on-chip flash memory, 512 bytes of ram ? internal clock generator module (icg) ? two 16-bit, 2-channel timers ? 10-bit analog-to-digital converter (adc) ? lin physical layer interface ? autonomous mcu watchdog / mcu supervision ? one analog input with switchable current source ? four low rds(on) half-bridge outputs ? three low rds(on) high-side outputs ? ec glass driver circuitry ? wake-up input ? one 2/3-pin hall-effect sensor input ? 12 microcontroller i/os figure 1. 908e622 simplified application diagram quad half-bridge, triple high-side switch and ec glass circuitry with embedded mcu and lin 908e622 ordering information device temperature range (t a ) package MM908E622acdwb/r2 -40c to 85c 54 soicw-ep dwb suffix 98arl10519d 54-terminal soicw-ep rst_a rst irq_a irq vssa/vrefl lin vdda/vrefh evdd vdd evss vss l0 hs1 ecr vsup[1:8] a0 a0cst high side output 3 high side output 2 high side output 1 hs2 hs3 ec h0 hvdd gnd[1:4] ec - glas control switched 5v output analog input with current source analog input current source trim 2-/3-pin hall sensor input wake up input 4. 7 f >2 2f hb1 hb2 m m 4 x half bridge outputs hb3 m hb4 ptc2/mclk ptc3/osc2 ptc4/osc1 c portc ptb3/ad3 ptb4/ad4 ptb5/ad5 c portb pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 c porta pte1/rxd internally connected c porte ptd0/tach0 c portd ptd1/tach1 testmode pull to ground for user mode ep 100nf 100nf internally connected 908e622
analog integrated circuit device data 2 freescale semiconductor 908e622 internal block diagram internal block diagram m68hc08 cpu alu port b ddrb ptb0/ad0 adout analog multiplexer analog port with current source cpu registers ddre port e pte1/rxd pte0/txd ptb1/ad1 ptb2/ad2 ptb3/ad3 ptb4/ad4 ptb5/ad5 ptb6/ad6/tbch0 ptb7/ad7/tbch1 ddrd port d ptd1/tach1 ptd0/tach0 port c ddrc ptc4/osc1 ptc3/osc2 ptc2/mclk ptc1/mosi ptc0/miso bemf module prescaler module arbiter module periodic wake-up timebase module configuration register module serial peripheral interface module computer operating properly module enhanced serial communication interface module 2-channel timer interface module b 2-channel timer interface module a 5-bit keyboard interrupt module single breakpoint break module ddra port a pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 pta5/spsck pta6/ss security module power-on reset module power vss vdd 10 bit analog-to- digital converter module vssa vrefl vdda vrefh single external irq module irq 24 internal system integration module rst internal clock generator module osc1 osc2 user flash vector space, 36 bytes flash programming (burn-in), 1024 bytes monitor rom, 310 bytes user ram, 512 bytes user flash, 15,872 bytes control and status register, 64 bytes internal bus flsvpp ptd1/tach1 ptc4/osc1 ptc3/osc2 ptc2/mclk ptb5/ad5 ptb4/ad4 ptb3/ad3 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 vdda/vrefh evdd evss vssa/vrefl rst irq rst_a irq_a pte1/rxd ptd0/tach0 lin testmode vsup[1:8] gnd[1:4] ptb0/ad0 pta5/spsck spsck mosi ptc1/mosi miso ptc0/miso ss pwm pta6/ss ptd0/tach0 pte0/txd pte1/rxd rxd txd spi & control hallport ec glass driver & diagnostic half bridge driver & diagnostic half bridge driver & diagnostic half bridge driver & diagnostic half bridge driver & diagnostic high side driver & diagnostic high side driver & diagnostic high side driver & diagnostic autonomous watchdog reset control lin physical layer wakeup port voltage regulator switched vdd driver & diagnostic a0cst a0 h0 ec ecr hb4 hb3 hb2 hb1 hs3 hs2 hs1[a:b] l0 hvdd vdd vss figure 2. 908e622 simplifie d internal block diagram
analog integrated circuit device data freescale semiconductor 3 908e622 terminal connections terminal connections figure 3. terminal connections table 1. terminal definitions a functional description of each terminal can be found in the functional terminal description section beginning on page 21 . die terminal terminal name formal name definition mcu 1 2 3 ptc4/osc1 ptc3/osc2 ptc2/mclk port c i/os these terminals are special-f unction, bidirectional i/o port terminals that are shared with other functional modules in the mcu. mcu 4 5 6 ptb5/ad5 ptb4/ad4 ptb3/ad3 port b i/os these terminals are special-f unction, bidirectional i/o port terminals that are shared with other functional modules in the mcu. mcu 7 irq external interrupt input this terminal is an asynchronous external interrupt input terminal. mcu 8 rst external reset this terminal is bidirect ional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. mcu / analog 9 (ptd0/tach0/bemf -> pwm) pwm signal this terminal is the pwm signal test terminal. it internally connects the mcu ptd0/tach0 terminal with the analog die pwm input. note: do not connect in the application. mcu 10 ptd1/tach1 port d i/os this terminal is a special- function, bidirectional i/o port terminal that is shared with other functional modules in the mcu. mcu / analog 44 (pte1/rxd <- rxd) lin transceiver output this terminal is the lin transceiver output test terminal. it internally connects the mcu pte1/rxd term inal with the analog die lin transceiver output terminal rxd. note: do not connect in the application. pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 vdda/vrefh evdd evss vssa/vrefl (pte1/rxd <- rxd) vss vdd hvdd l0 h0 hs3 vsup8 hs2 vsup7 hs1b hs1a vsup6 vsup5 gnd4 hb1 vsup4 flsvpp ptc4/osc1 ptc3/osc2 ptc2/mclk ptb5/ad5 ptb4/ad4 ptb3/ad3 irq rst (ptd0/tach0/bemf -> pwm) ptd1/tach1 rst_a irq_a lin a0cst a0 gnd1 hb4 vsup1 gnd2 hb3 vsup2 ec ecr testmode gnd3 hb2 vsup3 1 11 12 13 14 15 16 17 18 19 20 9 10 21 22 23 24 25 26 27 6 7 8 4 5 2 3 54 44 43 42 41 40 39 38 37 36 35 46 45 34 33 32 31 30 29 28 49 48 47 51 50 53 52 exposed pad transparent top view of package
analog integrated circuit device data 4 freescale semiconductor 908e622 terminal connections mcu 45 48 vssa/vrefl vdda/vrefh adc supply and reference terminals these terminals are the power supply and voltage reference terminals for the analog-to-digital converter (adc). mcu 46 47 evss evdd mcu power supply terminals these terminals are the ground and power supply terminals, respectively. the mcu operates from a single power supply. mcu 49 50 52 53 54 pta4/kbd4 pta3/kbd3 pta2/kbd2 pta1/kbd1 pta0/kbd0 port a i/os these terminals are special-f unction, bidirectional i/o port terminals that are shared with other functional modules in the mcu. mcu 51 flsvpp test terminal for test purposes only. do not connect in the application. analog 11 rst_a internal reset this terminal is the bidirectional reset terminal of the analog die. analog 12 irq_a internal interrupt output this terminal is the interrupt output terminal of the analog die indicating errors or wake-up events. analog 13 lin lin bus this terminal represents the single-wire bus transmitter and receiver. analog 14 a0cst analog input trim terminal this is the analog input trim terminal for the a0 input. this is to connect a known fixed resistor val ue to trim the current source measurement. analog 15 a0 analog input terminal this terminal is an analog input port with selectable source values. analog 16 19 25 30 gnd1 gnd2 gnd3 gnd4 power ground terminals these terminals are device power ground connections. analog 29 26 20 17 hb1 hb2 hb3 hb4 half-bridge outputs this device includes power mosfets configured as four half-bridge driver outputs. these outputs may be configured for dc motor drivers, or as high-side and low-side switches. note: the hb3 and hb4 have a lower r ds(on) then hb1 and hb2. analog 18 21 27 28 31 32 35 vsup1 vsup2 vsup3 vsup4 vsup5 vsup6 vsup7 power supply terminals these terminals are devic e power supply terminals. analog 22 23 ec ecr ec glass terminal ec ballast resistor terminal these are the electrochrome circuitr y terminals. the ec terminal has to be connected to the ec glass and the ecr terminal has to be connected to the external ballast resistor. analog 24 testmode testmode input terminal for test pur pose only. in application this terminal needs to be tied gnd. analog 34 35 hs1a hs1b high-side hs1 output this output terminal is a low r ds(on) high-side switch. analog 36 38 hs2 hs3 high-side hs2 output high-side hs3 output these output terminals are low r ds(on) high-side switches. analog 39 h0 hall-effect sensor / general purpose input this terminal provides an input fo r a hall-effect sensor or general purpose input. analog 40 l0 wake-up input this terminal provides an high voltage input, which is wake-up capable. table 1. terminal definitions (continued) a functional description of each terminal can be found in the functional terminal description section beginning on page 21 . die terminal terminal name formal name definition
analog integrated circuit device data freescale semiconductor 5 908e622 terminal connections analog 41 hvdd switchable v dd output this terminal is a switchable v dd output for driving resistive loads requiring a regulated 5.0 v supply; e.g. potentiometers. analog 42 vdd voltage regulator output the +5.0 v voltage regulator output terminal is intended to supply the embedded microcontroller. analog 43 vss voltage regulator ground ground terminal for the connection of all non-power ground connections (microcontroller and sensors). ? ep exposed pad exposed pad the exposed pad termi nal on the bottom side of the package conducts heat from the chip to the pcb board. table 1. terminal definitions (continued) a functional description of each terminal can be found in the functional terminal description section beginning on page 21 . die terminal terminal name formal name definition
analog integrated circuit device data 6 freescale semiconductor 908e622 maximum ratings maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise noted. exceeding limits on any terminal may cause permanent damage to the device. rating symbol value unit electrical ratings supply voltage analog chip supply voltage under normal operation (steady-state) analog chip supply voltage under transient conditions (1) mcu chip supply voltage v sup(ss) v sup( pk ) v dd -0.3 to 28 -0.3 to 40 -0.3 to 5.5 v input terminal voltage analog chip microcontroller chip v in(analog) v in(mcu) -0.3 to 5.5 v ss -0.3 to v dd +0.3 v maximum microcontroller current per terminal all terminals except vdd, vss, pta0:pta4 pta0:pta4 i pin(1) i pin(2) 15 25 ma maximum microcontroller vss output current i mvss 100 ma maximum microcontroller vdd input current i mvdd 100 ma lin supply voltage normal operation (steady-state) transient input voltage (per iso7637 specification) and with external components (figure 4 , page 18 ) v bus(ss) v bus( pk ) -18 to 40 -150 to 100 v esd voltage human body model (2) h0 terminal human body model (2) all other terminals machine model (3) charge device model (4) v esd1-1 v esd1-2 v esd2 v esd3 1000 2000 200 750 v notes 1. transient capability for pulses with a time of t < 0.5 sec. 2. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap =1500 ? ). 3. esd2 testing is performed in ac cordance with the machine model (c zap =200 pf, r zap =0 ? ). 4. esd3 testing is performed in accordanc e with charge device model, robotic (c zap =4.0 pf).
analog integrated circuit device data freescale semiconductor 7 908e622 maximum ratings thermal ratings operating ambient temperature (5) t a -40 to 85 c operating junction temperature (6) t j -40 to 125 c storage temperature t stg -40 to 150 c peak package reflow temperature during solder mounting (7) t solder 245 c notes 5. the limiting factor is junction temperat ure; taking into account the power dissipat ion, thermal resistance, and heat sinking. 6. the temperature of analog and mcu die is strongly linked via the package, but can di ffer in dynamic load conditions, usually because of higher power dissipation on the analog die. the analog die temperature must not exceed 150c under these conditions. 7. terminal soldering temperature is for 10 seconds maximum duration. not designed for immersion soldering. exceeding these limi ts may cause malfunction or permanent damage to the device. table 2. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. exceeding limits on any terminal may cause permanent damage to the device. rating symbol value unit
analog integrated circuit device data 8 freescale semiconductor 908e622 static electrical characteristics static electrical characteristics table 3. static electr ical characteristics all characteristics are for the analog chip only. refer to th e 68hc908ey16 datasheet for charac teristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit supply voltage range nominal operating voltage v sup1 9.0 ? 16 v extended operating voltage (lin only 8..18v) (9) v sup2 7.5 ? 20 v supply current range normal mode (9) v sup = 12 v, analog chip in normal mode (pson=1), mcu operating using internal oscillator at 32 mhz (8.0 mhz bus frequency), spi, esci, adc enabled stop mode (9) , (10) v sup = 12 v, voltage regulator with limited current capability sleep mode (9) , (10) v sup = 12 v, voltage regulator off i run i stop i sleep ? ? ? 25 40 12 ? 50 20 ma a a digital interface ratings (analog die) output terminals rst_a , irq_a , rxd (miso probe only) low-state output voltage (i out = -1.5 ma) high-state output voltage ( iout = 250 ua) v ol v oh ? 3.85 ? ? 0.4 ? v output terminal rxd - capacitance (11) c out ?4.0?pf input terminals rst_a , pwm (ss , mosi, txd probe only) input logic low voltage input logic high voltage v il v ih ? 3.5 ? ? 1.5 ? v input terminals - capacitance (11) c in ?4.0?pf terminals irq_a , rst_a - pullup resistor r pullup1 ?10?kohm terminals ss - pullup resistor r pullup2 ?100?kohm terminals mosi, spsck, pwm - pull-down resistor r pulldown ?100?kohm terminal txd - pullup current source i pullup ?35? a notes 8. device is fully functional, but some of the parameters might be out of spec. 9. total current measured at gnd terminals. 10. stop and sleep mode current will increase if v sup exceeds 15 v. 11. this parameter is guaranteed by process monitoring but is not production tested.
analog integrated circuit device data freescale semiconductor 9 908e622 static electrical characteristics system resets and interrupts low voltage reset (lvr) threshold hysteresis v lvron v lvr_hys 3.8 50 4.2 ? 4.65 300 v mv low voltage interrupt (lvi) threshold hysteresis v lvion v lvi_hys 6.0 0.3 ? ? 7.5 0.8 v high voltage interrupt (hvi) threshold hysteresis v hvion v hvi_hys 20 0.5 ? ? 24 1.5 v high temperature interrupt (hti) (12) threshold t j hysteresis t ion t ih 125 5.0 ? ? 150 10.0 c high temperature reset (htr) (12) threshold t j hysteresis t ron t ih 155 5.0 ? ? 180 10.0 c voltage regulator (13) normal mode output voltage (14) i out = 60 ma, 7.5v < v sup < 20v i out = 60 ma, v sup < 7.5v and v sup > 20v v ddrun1 v ddrun2 4.75 4.75 5.0 5.0 5.25 5.25 v normal mode total output current i outrun ?120150ma load regulation - i out = 60 ma, v sup = 9v, t j = 125 cv lr ??100mv stop mode output voltage (14) v ddstop 4.75 5.0 5.25 v stop mode total output current i outstop 150 500 850 ua notes 12. this parameter is guaranteed by process monitoring but is not production tested. 13. specification with external low esr ceramic capacitor 1.0 f< c < 4.7 f and 200 m ? esr 10 ? . its not recommended to use capacitor values above 4.7 f 14. when switching from normal to stop mode or from stop mode to no rmal mode, the output voltage can vary within the output volt age specification. table 3. static electrical characteristics (continued) all characteristics are for the analog chip only. refer to th e 68hc908ey16 datasheet for charac teristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 908e622 static electrical characteristics lin physical layer lin transceiver output voltage recessive state, txd high, i out = 1.0 a dominant state, txd low, 500 ? external pullup resistor v lin_rec v lin_dom v sup -1 ? ? ? ? 1.4 v normal mode pullup resistor to vsup r pu 20 30 47 k ? stop, sleep mode pullup current source i pu ?20? a output current shutdown threshold i blim 100 230 280 ma output current shutdown timing i bls 5.0 ? 40 s leakage current to gnd v sup disconnected, v bus at 18v recessive state, 8v v sup 18v, 8v v bus 18v, v bus v sup gnd disconnected, v gnd = v sup , v bus at -18v i bus i bus-pas-rec i bus-nognd ? 0.0 -1.0 1.0 3.0 ? 10 20 1.0 a a ma lin receiver receiver threshold dominant receiver threshold recessive receiver threshold center receiver threshold hysteresis v bus_dom v bus_rec v bus_cnt v bus_hys ? 0.6 0.475 ? ? ? 0.5 ? 0.4 ? 0.525 0.175 vsup table 3. static electrical characteristics (continued) all characteristics are for the analog chip only. refer to th e 68hc908ey16 datasheet for charac teristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 908e622 static electrical characteristics high-side output hs1 switch on resistance t j = 25 c, i load = 1.0 a r ds(on)-hs1 ?185225 m ? overcurrent shutdown i hsoc1 6.0 ? 9.0 a overcurrent shutdown blanking time (15) t ocb ?4-8?s current to voltage ratio (16) v adout [v] / i hs [a], (measured and trimmed i hs = 2 a) cr ratiohs1 0.84 1.2 1.56 v/a high-side switching frequency (15) f pwmhs ??25khz high-side free-wheeling diode forward voltage t j = 25 c, i load = 1 a v hsf ?0.9?v leakage current i leakhs ?<0.210a high-side outputs hs2 and hs3 (17) switch on resistance t j = 25 c, i load = 1.0 a r ds(on)-hs23 ?440500 m ? overcurrent shutdown i hsoc23 3.6 ? 5.6 a overcurrent shutdown blanking time (15) t ocb ?4-8?s current to voltage ratio (16) v adout [v] / i hs [a], (measured and trimmed i hs = 2 a) cr ratiohs23 1.16 1.66 2.16 v/a high-side switching frequency (15) f pwmhs ??25khz high-side free-wheeling diode forward voltage t j = 25 c, i load = 1 a v hsf ?0.9?v leakage current i leakhs ?<0.210a notes 15. this parameter is guaranteed by process monitoring but is not production tested. 16. this parameter is guaranteed only if correct trimming was applied. 17. the high-side hs3 can be only used for resistive loads. table 3. static electrical characteristics (continued) all characteristics are for the analog chip only. refer to th e 68hc908ey16 datasheet for charac teristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 908e622 static electrical characteristics half-bridge outputs hb1 and hb2 switch on resistance high-side, t j = 25 c, i load = 1.0 a low-side, t j = 25 c, i load = 1.0 a r ds(on)-hb12 ? ? 750 750 900 900 m ? overcurrent shutdown high-side low-side i hboc12 1.0 1.0 ? ? 1.5 1.5 a overcurrent shutdown blanking time (18) t ocb ?4-8? s switching frequency (18) f pwm ??25 khz free-wheeling diode forward voltage high-side, t j = 25 c, i load = 1.0 a low-side, t j = 25 c, i load = 1.0 a v hsf v lsf ? ? 0.9 0.9 ? ? v leakage current i leakhb ?<0.210a low-side current to voltage ratio (19) v adout [v] / i hb [a], csa = 1, (measured and trimmed i hs = 200 ma) v adout [v] / i hb [a], csa = 0, (measured and trimmed i hs = 500 ma) cr ratiohb12 17.5 3.5 25.0 5.0 32.5 6.5 v/a half-bridge outputs hb3 and hb4 switch on resistance high-side, t j = 25 c, i load = 1.0 a low-side, t j = 25 c, i load = 1.0 a r ds(on)-hb34 ? ? 275 275 325 325 m ? overcurrent shutdown high-side low-side i hboc34 4.8 4.8 ? ? 7.2 7.2 a overcurrent shutdown blanking time (18) t ocb ?4-8? s switching frequency (18) f pwm ??25 khz free-wheeling diode forward voltage high-side, t j = 25 c, i load = 1.0 a low-side, t j = 25 c, i load = 1.0 a v hsf v lsf ? ? 0.9 0.9 ? ? v leakage current i leakhb ?<0.210a low-side current to voltage ratio (19) v adout [v] / i hb [a], csa = 1, (measured and trimmed i hs = 500 ma) v adout [v] / i hb [a], csa = 0, (measured and trimmed i hs = 2 a) cr ratiohb34 3.5 0.7 5.0 1.0 6.5 1.3 v/a notes 18. this parameter is guaranteed by process monitoring but is not production tested. 19. this parameter is guaranteed only if correct trimming was applied table 3. static electrical characteristics (continued) all characteristics are for the analog chip only. refer to th e 68hc908ey16 datasheet for charac teristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 908e622 static electrical characteristics ec outputs ec and ecr switch on resistance t1 measured on ecr terminal, t j = 25 c, i load = 100 ma t2 measured on ec terminal, t j = 25 c, i load = 100 ma r ds(on)t1 r ds(on)t2 ? ? 1.0 400 1.2 600 ? m ? overcurrent shutdown t1 (short to gnd) t2 (short to vsup) i t1oc i t2oc 0.6 0.6 ? ? 1.0 1.0 a open load detection (bit ecolt is set) set @min output load r oc ?10?k ? dac resolution (from 0v to 1.4v) ec dacres ?6.0?bit regulated output voltage (@ i = 1ma) vec reg 0.18 ? 1.4 v switchable v dd output hvdd overcurrent shutdown i hvddoc 25 35 50 ma overcurrent shutdown blanking time (20) hvddt1:0 = 00 hvddt1:0 = 01 hvddt1:0 = 10 hvddt1:0 = 11 t hvddocb ? ? ? ? 950 536 234 78 ? ? ? ? s overcurrent flag delay (20) t hvddocfd ?0.5?ms drop-out voltage @ i load = 20 ma v hvdddrop ?110300mv v sup down scaler (21) voltage ratio (ratio vsup = v sup / v adout )ratio vsup 4.75 5.0 5.25 ? internal die temperature sensor (21) voltage / temperature slope (20) s ttov ?26?mv/c output voltage @25c v t25 1.7 1.9 2.1 v notes 20. this parameter is guaranteed by process monitoring but is not production tested. 21. this parameter is guaranteed only if correct trimming was applied table 3. static electrical characteristics (continued) all characteristics are for the analog chip only. refer to th e 68hc908ey16 datasheet for charac teristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 908e622 static electrical characteristics hall-effect sensor input h0 - general purpose input mode (h0ms = 0) input voltage low threshold v lt ??1.5v input voltage high threshold v ht 3.5 ? ? v input voltage hysteresis v hh 100 ? 500 mv pullup resistor r ph 7.0 10 13 k ? hall-effect sensor input h0 - 2pin hall sensor input mode (h0ms = 1) output voltage v sup < 17v v sup >17v v hall1 v hall2 ? ? v sup -1.2 ? ? 15.8 v output drop @ i out = 15ma v h0d ??2.5v sense current threshold i hsct 6.0 7.9 10 ma sense current hysteresis i hsch 800 1100 1650 a sense current limitation v hsclim 20 40 70 ma analog input a0, a0cst current source a0, a0cst (22) (23) cssel1:0 = 00 cssel1:0 = 01 cssel1:0 = 10 cssel1:0 = 11 i cs1 i cs2 i cs3 i cs4 ? ? ? ? 40 120 320 800 ? ? ? ? a wake-up input l0 input voltage threshold low v lt ??1.5v input voltage threshold high v ht 3.5 ? ? v input voltage hysteresis v lh 0.5 ? ? v input current i n -10 ? 10 a wake-up filter time (24) t wup ?20?s notes 22. this parameter is guaranteed only if correct trimming was applied 23. the current values are optimized to read a ntc temperature sensor, e.g. epcos type b57861 (r25 = 3000 ?, r/t characteristic 8016) 24. this parameter is guaranteed by process monitoring but is not production tested. table 3. static electrical characteristics (continued) all characteristics are for the analog chip only. refer to th e 68hc908ey16 datasheet for charac teristics of the microcontroller chip. characteristics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 908e622 dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electr ical characteristics all characteristics are for the analog chip only. please re fer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteri stics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit lin physical layer driver characteristics for normal slew rate (25) , (26) dominant propagation delay txd to lin t dom- min ??50 s dominant propagation delay txd to lin t dom- max ??50 s recessive propagation delay txd to lin t rec- min ??50 s recessive propagation delay txd to lin t rec- max ??50 s duty cycle 1: d1 = t bus_rec(min) / (2 x t bit ), t bit = 50 s, v sup = 7.0v..18v d1 0.396 ? ? duty cycle 2: d2 = t bus_rec(max) / (2 x t bit ), t bit = 50 s, v sup = 7.6v..18v d2 ? ? 0.581 driver characteristics for slow slew rate (25) , (27) dominant propagation delay txd to lin t dom- min ? ? 100 s dominant propagation delay txd to lin t dom- max ? ? 100 s recessive propagation delay txd to lin t rec- min ? ? 100 s recessive propagation delay txd to lin t rec- max ? ? 100 s duty cycle 3: d3 = t bus_rec(min) / (2 x t bit ), t bit = 96 s, v sup = 7.0v..18v d3 0.417 ? ? duty cycle4: d4 = t bus_rec(max) / (2 x t bit ), t bit = 96 s, v sup = 7.6v..18v d4 ? ? 0.590 driver characteristics for fast slew rate lin high slew rate (programming mode) sr fast ?20?v/ s receiver characteristics and wake-up timings receiver dominant propagation delay (28) t rl ?3.56.0 s receiver recessive propagation delay (28) t rh ?3.56.0 s receiver propagation delay symmetry t r-sym -2.0 ? 2.0 s bus wake-up deglitcher t propwl 30 50 150 s bus wake-up event reported (29) t wake ?20? s notes 25. v sup from 7.0 v to 18 v, bus load r0 and c0 1.0 nf/1.0 k ? , 6.8 nf/660 ? , 10 nf/500 ? . measurement thresholds: 50% of txd signal to lin signal threshold defined at each parameter. 26. see figure 6 , page 18 . 27. see figure 7 , page 19 . 28. measured between lin signal threshold v il or v ih and 50% of rxd signal. 29. t wake is typically 2 internal clock cycles after lin rising edge detected. see figure 9 and figure 8 , page 19 . in sleep mode the v dd rise time is strongly dependent upon the dec oupling capacitor at vdd terminal.
analog integrated circuit device data 16 freescale semiconductor 908e622 dynamic electrical characteristics spi interface timing spi operating recommended frequency (30) f spiop 0.25 ? 4.0 mhz state machine reset low-level duration after vdd high t rst 0.8 1.25 1.94 ms normal request time-out t normreq 51 80 124 ms window watchdog timer (31) watchdog period (wdp1:0 = 00) t wd80 52 80 124 ms watchdog period (wdp1:0 = 01) t wd40 26 40 62 ms watchdog period (wdp1:0 = 10) t wd20 13 20 31 ms watchdog period (wdp1:0 = 11) t wd10 6.5 10 15.5 ms notes 30. this parameter is guaranteed by process monitoring but is not production tested. 31. this parameter is guaranteed only if correct trimming was applied. additionally see watchdog period range value (awd trim) on page 51 table 4. dynamic electrical characteristics (continued) all characteristics are for the analog chip only. please re fer to the 68hc908ey16 datasheet for characteristics of the microcontroller chip. characteri stics noted under conditions 9.0 v v sup 16 v, -40 c t j 125 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 17 908e622 microcontroller parametrics microcontroller parametrics table 5. microcontroller for a detailed microcontroller description, refer to the mc68hc908ey16 datasheet. module description core high performance hc08 core with a maximum internal bus frequency of 8.0 mhz timer two 16-bit timers with 2 channels (tim a and tim b) flash 16 k bytes ram 512 bytes adc 10-bit analog-to-digital converter spi spi module esci standard serial communication interface (sci) module bit-time measurement arbitration prescaler with fine baud-rate adjustment icg internal clock generation module
analog integrated circuit device data 18 freescale semiconductor 908e622 timing diagrams timing diagrams figure 4. test circuit for transient test pulses figure 5. test circuit for lin timing measurements figure 6. lin timing meas urements for normal slew rate lin, l0 10k 1nf transient pulse generator note: waveform in accordance to iso7637 part 1, test pulses 1, 2, 3a and 3b. r0 c0 vsup rxd txd lin r0 and c0 combinations: - 1k ohm and 1nf - 660 ohm and 6.8nf - 500 ohm and 10nf r0 and c0 combinations: ? 1.0 k ? and 1.0 nf ? 600 ? and 6.8 nf ? 500 ? and 10 nf v sup t dom-min t dom-max t rl txd lin rxd t rh t rec-min t rec-max 58.1% v sup 40% v sup 28.4% v sup 42.2% v sup 60% v sup 74.4% v sup v lin
analog integrated circuit device data freescale semiconductor 19 908e622 timing diagrams figure 7. lin timing measurements for slow slew rate figure 8. wake-up stop mode timing figure 9. wake-up sleep mode timing t dom-min t dom-max t rl txd lin rxd v lin t rh t rec-min t rec-max 61.6% v sup 40% v sup 25.1% v sup 38.9% v sup 60% v sup 77.8% v sup irq_a lin vrec tpropwl twake dominant level 0.4vsup t propwl t wake dominant level 0.4 v sup v lin_rec vdd lin vrec tpropwl twake dominant level 0.4vsup v lin_rec 0.4 v sup dominant level t propwl t wake
analog integrated circuit device data 20 freescale semiconductor 908e622 timing diagrams figure 10. power on reset and normal request time-out timing v sup t rst v dd rst_a t normreq
analog integrated circuit device data freescale semiconductor 21 908e622 functional description introduction functional description introduction the 908e622 was designed and developed as a highly integrated and cost-effective solution for automotive and industrial applications. for automotive body electronics, the 908e622 is well suited to perform complete mirror control via a three-wire lin bus. this device combines an hc908ey16 mcu core with flash memory together with a smartmos ic chip. the smartmos ic chip combines power and control in one chip. power switches are provided on the smartmos ic configured as half-bridge outputs and three high-side switches. other ports are also provided, which include a circuitry for ec-glass control, one hall-effect sensor input port, one analog input port with a switched current source, one wake-up terminal, and a selectable hvdd terminal. an internal voltage regulator provides power to the mcu chip. also included in this device is a lin physical layer, which communicates using a single wire. this enables this device to be compatible with three-wir e bus systems, where one wire is used for communication, one for battery, and one for ground. functional terminal description see figure 2, 908e622 simplified internal block diagram , page 2 , for a graphic representation of the various terminals referred to in the following paragraphs. also, see the terminal diagram on page 3 for a depiction of the terminal locations on the package. port a i/o terminals these terminals are special-function, bidirectional i/o port terminals that are shared with other functional modules in the mcu. pta0:pta4 are shared with the keyboard interrupt terminals, kbd0:kbd4. the pta5/spsck terminal is not accessible in this device and is internally connected to the spi clock terminal of the analog die. the pta6/ ss terminal is not accessible in this device and is internally connected to the spi slave select input of the analog die. for details refer to the 68hc908ey16 datasheet. port b i/o terminals these terminals are special-function, bidirectional i/o port terminals that are shared with other functional modules in the mcu. all terminals are sh ared with the adc module. ptb0/ad0 is internally connected to the adout terminal of the analog die, allowing diagnostic measurements to be calculated; e.g., current recopy, v sup , etc. the ptb1/ad1, ptb2/ad2, ptb6/ad6/tbch0, ptb7/ ad7/tbch1 terminals are not accessible in this device. for details refer to the 68hc908ey16 datasheet. port c i/o terminals these terminals are special-function, bidirectional i/o port terminals that are shared with other functional modules in the mcu. for example, ptc2:ptc4 are shared with the icg module. ptc0/miso and ptc1/mosi are not accessible in this device and are internally connected to the miso and mosi spi terminals of the analog die. for details refer to the 68hc908ey16 datasheet. port d i/o terminals ptd0/tach0/bemf and ptd1/tach1 are special- function, bidirectional i/o port terminals that can also be programmed to be timer terminals. ptd0/tach0 terminal is internally connected to the pwm input of the analog die and only accessible for test purposes (can not be used in the application). for details refer to the 68hc908ey16 datasheet. port e i/o terminal pte0/txd and pte1/rxd are special-function, bidirectional i/o port terminals that can also be programmed to be enhanced serial communication. pte0/txd is internally connected to the txd terminal of the analog die. the connection for the receiver must be done externally. pte1/rxd is internally connected to the rxd terminal of the analog die and only accessible for test purposes (can not be used in the application). for details refer to the 68hc908ey16 datasheet. external interrupt terminal ( irq ) the irq terminal is an asynchronous external interrupt terminal. this terminal contains an internal pullup resistor that is always activated, even when the irq terminal is pulled low. for details refer to the 68hc908ey16 datasheet.
analog integrated circuit device data 22 freescale semiconductor 908e622 functional description functional terminal description external reset terminal ( rst ) a logic [0] on the rst terminal forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. this terminal contains an inte rnal pullup resistor that is always activated, even when the reset terminal is pulled low. for details refer to the 68hc908ey16 datasheet. power supply terminals (vsup1:vsup8) vsup1:vsup8 are device power supply terminals. the nominal input voltage is designed for operation from 12 v systems. owing to the low on-resistance and current requirements of the half-bridge driver outputs and high-side output drivers, multiple vsu p terminals are provided. all vsup terminals must be co nnected to get full chip functionality. power ground terminals (gnd1:gnd4) gnd1:gnd4 are device power ground connections. owing to the low on-resistance and current requirements of the half-bridge driver outputs and high-side output drivers, multiple terminals are provided. gnd1 and gnd2 terminals must be connected to get full chip functionality. half-bridge output terminals (hb1:hb4) the 908e622 device includes power mosfets configured as four half-bridg e driver outputs. the hb3:hb4 have a lower r ds(on) , to run higher curren ts (e.g. fold motor), than the hb1:b2 outputs. the hb1:hb4 outputs are short-circuit and overtemperature protected, and they feature current recopy. over current protection is done on both high-side and low- side fet?s. the current recopy are done on the low-side mosfets. high-side output terminals (hs1:hs3) the hs output terminals are a low r ds(on) high-side switches. each hs switch is protected against overtemperature and overcurrent. the output is capable of limiting the inrush current with an automatic pwm or feature a real pwm capability using the pwm input. the hs1 has a lower r ds(on) , to run higher currents (e.g. heater), than the hs2 and hs3 outputs. for the hs1 two terminals (hs1a:hs1b) are necessary for the current capability and have to be connected externally. important: the hs3 can be only used to drive resistive loads. ec glass terminals (ecr, ec) these terminals are used to drive the electrochrome function on ec glass mirrors. the ecr terminal is used to connect an external ballast resistor. the ec terminal provides the mirror with an regulated output voltage up to 1.4v. the output voltage can be selected by an integrated da converter. hall-effect sensor input terminal (h0) the hall-effect sensor input terminal h0 provides an input for hall-effect sensors (2pin or 3pin) or a switch. analog input terminals (a0, a0cst) these terminals are analog inputs with selectable current source values. the a0cst is intent to trim the a0 input. wake-up input terminal (l0) this terminal is 40v rated input. it can be used as wake-up source for a system wake-up. the input is falling or rising edge sensitive. important: if unused this terminal should be connected to vsup or gnd to avoid parasitic transitions. in low power mode this could lead to random wake-up events. switchable v dd output terminal (hvdd) the hvdd terminal is a switchable v dd output for driving resistive loads requiring a r egulated 5.0 v supply; e.g., 3-terminal hall-effect sensors or potentiometers. the output is short-circuit protected. lin bus terminal (lin) the lin terminal represents the single-wire bus transmitter and receiver. it is suited for automotive bus systems and is based on t he lin bus specification. +5.0 v voltage regulator output terminal (vdd) the vdd terminal is needed to place an external capacitor to stabilize the regulated outp ut voltage. the vdd terminal is intended to supply the embedded microcontroller. important the vdd terminal should not be used to supply other loads; use the hvdd terminal for this purpose. the vdd, evdd and vdda/vrefh terminals must be connected together. voltage regulator ground terminal (vss) the vss terminal is the ground terminal for the connection of all non-power ground connections (microcontroller and sensors). important vss, evss and vssa/vrefl terminals must be connected together.
analog integrated circuit device data freescale semiconductor 23 908e622 functional description functional terminal description reset terminal ( rst_a ) rst_a is the bidirectional reset terminal of the analog die. it is an open drain with pullup resistor and must be connected to the rst terminal of the mcu. interrupt terminal ( irq_a ) irq_a is the interrupt output terminal of the analog die indicating errors or wake-up events. it is an open drain with pullup resistor and must be connected to the irq terminal of the mcu. adc supply/reference terminals (vdda/ vrefh and vssa/vrefl) vdda and vssa are the power supply terminals for the analog-to-digital converter (adc). vrefh and vrefl are the reference voltage terminals for the adc. the supply and reference signals are internally connected. it is recommended that a high quality ceramic decoupling capacitor be placed between these terminals. for details refer to the 68hc908ey16 datasheet. mcu power supply terminals (evdd and evss) evdd and evss are the power supply and ground terminals. the mcu operates from a single power supply. fast signal transitions on mcu terminals place high, short- duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu. for details refer to the 68hc908ey16 datasheet. test mode terminal (testmode) this terminal is for test purpose only. in the application this terminal has to be forced to gnd. for programming/test this terminal has to be forced to vdd to bring the analog die into test mode. in test mode the reset time-out (80ms) is disa bled and the lin receiver is disabled note: after detecting a reset (internal or external) the pson bit needs to be set within 80ms. if not the device will automatically enter sleep mode. mcu test terminal (flsvpp) this terminal is for test purposes only. this terminal should be either left open (not conne cted) or can be connected to gnd. exposed pad terminal the exposed pad terminal on the bottom side of the package conducts heat from the chip to the pcb board. for thermal performance the pad must be soldered to the pcb board. it is recommended that the pad be connected to the ground potential. 4,7f 0,1f vdda/vrefh evdd evss vssa/vrefl vdd vss c analog die
analog integrated circuit device data 24 freescale semiconductor 908e622 functional device operation operational modes functional device operation operational modes 908e622 analog die modes of operation the 908e622 offers three operating modes: normal (run), stop, and sleep. in normal mode the device is active and is operating under normal application conditions. the stop and sleep modes are low power modes with wake-up capabilities. the different modes can be selected by the stop and sleep bits in the system control register. figure 11 describes how transitions are done between the different operating modes and table 6 , page 26 , gives an overview of the operating modes. figure 11. operating modes and transitions normal mode this mode is normal operating mode of the device, all functions and power stages are active and can be enabled/ disabled. the voltage regulator provides the +5v v dd to the mcu. after a reset (e.g. power on reset, wake-up from sleep) the mcu has to set the pson bit in the system control register within 80ms typical (t normreq ), this is to ensure the mcu has started up and is operating correctly. if the pson bit is not set within the required time frame the device is entering sleep mode to reduce power consumption (fail safe). this mcu monitoring can be disabled e.g. for programming by applying v dd on the testmode terminal. stop mode in stop mode the voltage regulator still supplies the mcu with v dd (limited current capability). to enter the stop mode the stop bit in the system control register has to be set and the mcu has to be stopped also (see 908ey16 datasheet for details). wake-up from this mode is possi ble by lin bus activity or the wake-up input l0 and is maskable with the linie and/or l0ie bits in the interrupt mask register. the analog die is generating an interrupt on irq_a terminal to wake-up the mcu. the wake-up / interrupt source can be evaluated with the l0if and linif bits in the interrupt flag register. stop mode has a higher current consumption than sleep mode, but allows a quicker wake-up. additionally the wake- reset power down power up normal request v dd high and reset delay (t rst ) expired normal sleep wake-up (reset) stop reset (lvr, ext. reset, (htr)) sleep command stop command wake-up interrupt pson = 1 v dd low reset (lvr, htr, wdr, ext. reset) reset (lvr, ext. reset) testmode = 1 pson = 0 and normal request timeout (t normreq ) expired
analog integrated circuit device data freescale semiconductor 25 908e622 functional device operation operational modes up sources can be selected (maskable) which is not possible in sleep mode. figure 12 show the procedure to enter the stop mode and how the system is waking up. figure 12. stop mode wake-up procedure sleep mode in sleep mode the voltage regulator is turned off and the mcu is not supplied (v dd = 0 v) also the rst_a terminal is pulled low. to enter the sleep mode the sleep bit in the system control register has to be set. wake-up from this mode is possi ble by lin bus activity or the wake-up input l0 and is not maskable. the wake-up behaves like a power on reset. the wake-up / reset source can be evaluated by the l0wf and/or linwf bits in the reset status register. sleep mode has a lower current consumption than stop mode, but requires a longer time to wake-up. the wake-up sources can not be selected (not maskable). figure 13 show the procedure to enter the sleep mode and how a wake-up is performed. figure 13. sleep mode wake-up procedure table 6 summarized the operating modes. from reset initialize operate spi: stop =1 mcu stop irq interrupt ? spi: reason for interrupt switch to vreg low current mode assert irq switch to vreg high current mode mcu power die wake up on lin or l0 ? enable/disable lin/l0 wakeup from reset initialize operate spi: sleep =1 switch off vreg vdd low, rst low store wake up event start vreg vdd high, rst high mcu power die wake up on lin or l0 ?
analog integrated circuit device data 26 freescale semiconductor 908e622 functional device operation operational modes operating modes of the mcu for a detailed description of the operating modes of the mcu, refer to the mc68hc908ey16 datasheet. interrupts the 908e622 has seven different interrupt sources. an interrupt pulse on the irq_a terminal is generated to report an event or fault to the mcu. all interrupts are maskable and can be enabled/disabled via the spi (interrupt mask register). after reset all interrupts are automatically disabled. low voltage interrupt low voltage interrupt (lvi) is related to external supply voltage vsup. if this voltage falls below the lvi threshold, it will set the lvif bit in the interrupt flag register. in case the low voltage interrupt is enabled (lvie = 1), an interrupt will be initiated. during sleep and stop mode the low voltage interrupt circuitry is disabled. high voltage interrupt the high voltage interrupt (hvi) is related to the external supply voltage vsup. if this voltage rises above the hvi threshold it will set the hvif bit in the interrupt flag register. in case the high voltage interrupt is enabled (hvie = 1), an interrupt will be initiated. during stop and sleep mode the hvi circuitry is disabled. high temperature interrupt the high temperature interrupt (hti) is generated by the on chip temperature sensors. if the chip temperature is above the hti threshold the htif bit in the interrupt flag register will be set. in case the high temperature interrupt is enabled (htie = 1), an interrupt will be initiated. during stop and sleep mode the hti circuitry is disabled. lin interrupt the lin interrupt is related to the stop mode. if the lin interrupt is enabled (linie = 1) in stop mode an interrupt is asserted, if a rising edge is detected and the bus was dominant longer than t propwl . after the wake-up / interrupt the linif is indicati ng the reason for the wake-up / interrupt. power stage fail interrupt the power stage fail flag indicates an error condition on any of the power stages (see figure 14 , page 27 ). in case the power stage fail interrupt is enabled (psfie = 1), an interrupt will be initiated if: during stop and sleep mode the psfi circuitry is disabled. ho input interrupt the h0 interrupt flag h0if is set in run mode by a state change of the h0f flag (rising or falling edge on the enabled table 6. operating modes overview device mode voltage regulator wake-up capabilities rst_a output mcu monitoring/ watchdog function power stages lin interface reset v dd on n/a low disabled disabled disabled normal request v dd on n/a high t normreq (80 ms typical) time out to set pson bit in system control register disabled disabled normal (run) v dd on n/a high window watchdog active if enabled enabled enabled stop v dd on with limited current capability lin wake-up, l0 state change (spi pson=1) (1) high disabled disabled recessive state with wake-up capability sleep v dd off lin wake-up l0 state change low disabled disabled recessive state with wake-up capability notes 1. the spi is still active in stop mode. however, due to the limited current capability of the voltage regulator in stop mode, t he pson bit has to be set before the increased curr ent caused from a running mcu causes an lvr.
analog integrated circuit device data freescale semiconductor 27 908e622 functional device operation operational modes input). the interrupt function is available if the input is selected as general purpose or as 2pin hallsensor input. the interrupt is maskable with the h0ie bit in the interrupt mask register. during stop and sleep mode the h0i circuitry is disabled. l0 input interrupt the l0 interrupt flag l0if is set in run mode by a state change of the l0f flag (rising or falling edge). the interrupt is maskable with the l0ie bit in the interrupt mask register. interrupt flag register (ifr) l0if - l0 input flag bit this read/write flag is set on a falling or rising edge at the l0 input. clear l0if by writ ing a logic [1] to l0if. reset clears the l0if bit. writin g a logic [0] to l0if has no effect. 1 = rising or falling edge on l0 input detected 0 = no state change on l0 input detected h0if - h0 input flag bit this read/write flag is set on a falling or rising edge at the h0 input. clear h0if by writing a logic [1] to h0if. reset clears the h0if bit. writing a logic [0] to h0if has no effect. 1 = state change on the hallflags detected 0 = no state change on the hallflags detected linif - lin flag bit this read/write flag is set if a rising edge is detected and the bus was dominant longer than tpropwl. clear linif by writing a logic [1] to linif. reset clears the linif bit. writing a logic [0] to linif has no effect. 1 = lin bus interrupt has occurred 0 = not lin bus interrupt occurred since last clear htif - high temperature flag bit this read/write flag is set on high temperature condition. clear htif by writing a logic [1 ] to htif. if high temperature condition is still present while writing a logical one to htif, the writing has no effect. t herefore, a high temperature interrupt cannot be lost due to inadvertent clearing of htif. reset clears the htif bit. writing a logic [0] to htif has no effect. 1 = high temperature c ondition has occurred 0 = high temperature condition has not occurred lvif - low voltage flag bit this read/write flag is set on low voltage condition. clear lvif by writing a logic [1] to lvif. if low voltage condition is still present while writing a logica l one to lvif, the writing has no effect. therefore, a low vo ltage interrupt cannot be lost due to inadvertent clearing of lvif. reset clears the lvif bit. writing a logic [0] to lvif has no effect. 1 = low voltage condition has occurred 0 = low voltage condition has not occurred hvif - high voltage flag bit this read/write flag is set on high voltage condition. clear hvif by writing a logic [1] to hvif. if high voltage condition is still present while writing a logica l one to hvif, the writing has no effect. therefore, a high vo ltage interrupt cannot be lost due to inadvertent clearing of hvif. reset clears the hvif bit. writing a logic [0] to hvif has no effect. 1 = high voltage condition has occurred 0 = high voltage condition has not occurred psfif - power stage fail bit this read-only flag is set on a fail condition on one of the power outputs (hbx, hsx, hvdd, ec, h0). reset clears the psfif bit. clear this flag, by writing a logic [1] to the appropriate fail flag. 1 = power stage fail condition has occurred 0 = power stage fail condition has not occurred figure 14. principal implementation of the psfif register name and address: ifr - $0a bit7 6 5 4 3 2 1 bit0 read l0if h0if linif 0 htif lvif hvif psfif write reset 0 0 0 0 0 0 0 0 ecocf ecolf hs3oc hs2oc hs1oc hb4oc hb3oc hb2oc hb1oc hvddocf h0ocf hbff hsff hvddocf ecff h0ocf psfif
analog integrated circuit device data 28 freescale semiconductor 908e622 functional device operation operational modes interrupt mask register (imr) l0ie - l0 input interrupt enable bit this read/write bit enables cpu interrupts by the l0 flag, l0if. reset clears the l0ie bit. 1 = interrupt requests from l0if flag enabled 0 = interrupt requests from l0if flag disabled h0ie - h0 input interrupt enable bit this read/write bit enables cpu interrupts by the hallport flag, h0if. reset clears the h0ie bit. 1 = interrupt requests from h0if flag enabled 0 = interrupt requests from h0if flag disabled linie - lin line interrupt enable bit this read/write bit enables cpu interrupts by the lin flag, linif. reset clears the linie bit. 1 = interrupt requests from linif flag enabled 0 = interrupt requests from linif flag disabled htrd - high temperature reset disable bit this read/write bit disables the high temperature reset function. reset clears the htrd bit. 1 = high temperature reset is disabled 0 = high temperature reset is enabled note: disabling of the high temperature reset can lead to a destruction of the part in cases of high temperature. this bit was foreseen fo r test purposes only!!!!! htie - high temperatur e interrupt enable bit this read/write bit enables cpu interrupts by the high temperature flag, htif. reset clears the htie bit. 1 = interrupt requests from htif flag enabled 0 = interrupt requests from htif flag disabled lvie - low voltage interrupt enable bit this read/write bit enables cpu interrupts by the low voltage flag, lvif.reset clears the lvie bit. 1 = interrupt requests from lvif flag enabled 0 = interrupt requests from lvif flag disabled hvie - high voltage interrupt enable bit this read/write bit enables cpu interrupts by the high voltage flag, hvif.reset clears the hvie bit. 1 = interrupt requests from hvif flag enabled 0 = interrupt requests from hvif flag disabled psfie - power stage fail interrupt enable bit this read/write bit enables cpu interrupts by power stage fail flag, psfif. reset clears the psfie bit. 1 = interrupt requests from psfif flag enabled 0 = interrupt requests from psfif flag disabled register name and address: imr - $09 bit7 6 5 4 3 2 1 bit0 read l0ie h0ie linie htrd htie lvie hvie psfie write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data freescale semiconductor 29 908e622 functional device operation operational modes resets the 908e622 has four internal and one external reset source. each internal reset event will cause a reset pin low for t rst (1.25 ms typical), after the reset event is gone. figure 15. internal reset routing reset source high temperature reset the device is protected agai nst high temperature. when the chip temperature exceeds a certain temperature, a reset (htr) is generated. the reset is flagged by bit htr in the interrupt flag register. a htr event will reset all registers in the spi excluding the rsr. the htr can be disabled by bit htrd in the interrupt mask register. note: disabling the high temperature reset can lead to destruction of the part in cases of high temperature. this bit was foreseen for test purposes only! watchdog reset the watchdog module generates a reset, because of a watchdog time-out or wrong watchdog timer reset. reset is flagged by bit wdr in the reset status register. a watchdog reset event will reset all registers in the spi excluding the rsr. main vreg low voltage reset the lvr is related to the main vdd. in case the voltage falls below a certain threshold, it will pull down the rst_a terminal. reset is flagged by bit lvr in the reset status register. a lvr event will reset all register in the spi excluding the rsr. power on reset the por is related to the internal 5v supply. in case the device detects a power on the por bit in the reset status register (rsr) is set. a powe r on reset will reset all register in the spi including the rsr and set the por bit. the power on reset circuitry will force the rst_a terminal low for t rs t after the v dd has reached its nominal value (above lvr threshold). also see figure 10 , page 20 ). reset terminal / external reset an external reset can be applied by pulling down the rst_a terminal. the reset event is flagged by bit pinr in the reset status register. reset status register this register contains five fl ags that shows the source of the last reset. a power-on rese t sets the por bit and clears all other bits in the reset status register. all bits can be cleared by writing a one to the corresponding bit. uncleared bits remain set as long as they are not cleared by a power-on reset or by software. rsr wdre wd reset sensor vdd rst_a spi registers reset spi register (not rsr) por internal vreg lvr main vreg htrd htr reset sensor mono flop pulse duration after reset event is removed clear rsr and set por bit
analog integrated circuit device data 30 freescale semiconductor 908e622 functional device operation operational modes in addition the register includes two flags which will indicate the source of a wake-up from sleep mode: either lin bus activity or an event on the l0 wake-up input terminal. por? power on reset bit this read/write bit is set afte r power on. bit is cleared by writing a logic ?1? to this location. 1 = reset due to power on 0 = no power on reset pinr? reset forced from external reset terminal bit this read/write bit is set af ter an reset was forced on the external reset rst_a terminal. bit is cleared by writing an logic ?1? to this location. 1 = reset source is ex ternal reset terminal 0 = no external reset wdr? watch dog reset bit this read/write flag is set du e to watchdog time-out or wrong watchdog timer reset. clear wdr by writing a logic ?1? to wdr. 1 = reset source is watchdog 0 = no watchdog reset htr? high temperature reset bit this read/write bit is set if the chip temperature exceeds a certain value. bit is cleared by writing a logic ?1? to this location. 1 = reset due to high temperature condition 0 = no high temperature reset lvr? low voltage reset bit this read/write bit is set if the external vdd voltage coming from the main voltage regulator falls below a certain value. bit is cleared by writing a logic ?1? to this location. 1 = reset due to low voltage condition 0 = no low voltage reset linwf? lin wake-up flag this read/write bit is set if a bus activity was the case of an wake-up. bit is cleared by writing a logic ?1? to this location. 1 = wake-up due to bus activity 0 = no wake-up due to bus activity l0wf? l0 wake-up flag this read/write bit is set if a event on the l0 terminal caused an wake-up. bit is cleared by writing a logic ?1? to this location. 1 = wake-up due to l0 terminal 0 = no wake-up due to l0 terminal analog die inputs/outputs lin physical layer the lin bus terminal provides a physical layer for single- wire communication in automotive applications. the lin physical layer is designed to meet the lin physical layer specification. the lin driver is a low-side mosfet with internal current limitation and thermal shutdown. an internal pullup resistor with a serial diode structure is integrated, so no external pullup components are required for the application in a slave node. the fall time from dominant to recessive and the rise time from recessive to dominan t is controlled. the symmetry between both slew rate controls is guaranteed. the slew rate can be selected for optimized operation at 10 and 20kbit/s as well as high baud rates for test and programming. the slew rate can be adapted with 2 bits srs[1:0] in the system control register. the initial slew rate is optimized for 20kbit/s. the lin terminal offers high susceptibility immunity level from external disturbance, guaranteeing communication during external disturbance. the lin transmitter circuitry is enabled by setting the pson bit in the system control register (sysctl). if the transmitter works in th e current limitation region, the lincl bit in the system status register (sysstat) is set and the lin transceiver is disabled after a certain time. register name and address: rsr - $0d bit7 6 5 4 3 2 1 bit0 read por pinr wdr htr lvr 0 linwf lowf write por 1 0 0 0 0 0 0 0
analog integrated circuit device data freescale semiconductor 31 908e622 functional device operation operational modes for improved performance and safe behavior in case of lin bus short to ground or lin bus leakage during low power mode the internal pull-up resistor on the lin terminal is disconnected from vsup and a small current source keeps the lin bus at recessive level. in case of a lin bus short to gnd, this feature will reduce the current consumption in stop and sleep modes. figure 16. lin interface txd terminal the txd terminal is the mcu interface to control the state of the lin transmitter (see figure 2 , page 2 ). when txd is low, the lin terminal is low (dominant state). when txd is high, the lin output mosfet is turned off (recessive state). the txd terminal has an internal pullup current source in order to set the lin bus to rece ssive state in the event, for instance, the microcontroller could not control it during system power-up or power-down. rxd terminal the rxd transceiver terminal is the mcu interface, which reports the state of the lin bus voltage. lin high (recessive state) is reported by a high level on rxd, lin low (dominant state) by a low level on rxd. stop mode and wake-up feature during stop mode operation the transmitter of the physical layer is disabled and the internal pull-up resistor is disconnected from vsup and a small current source keeps the lin terminal in rece ssive state. the receiv er is still active and able to detect wake-up events on the lin bus line. if the lin interrupt is enabl ed (linie bit in the interrupt mask register is set), a dominant level longer than t propwl followed by an rising edge will set the linif flag and generate an interrupt which causes a system wake-up (see figure 8 , page 19 ) sleep mode and wake-up feature during sleep mode operation the transmitter of the physical layer is disabled and the internal pull-up resistor is disconnected from vsup and a small current source keeps the lin terminal in rece ssive state. the receiv er is still active to be able to detect wake-up events on the lin bus line. a dominant level longer than t propwl followed by an rising edge will generate a system wake-up (reset) and set the linwf flag in the reset status register (rsr). also see figure 9 , page 19 ). control receiver wakeup rxd txd gnd vsup slope control 30k 10a lin bus srs[1:0] pson lincl linif wakeup filter mode testmode
analog integrated circuit device data 32 freescale semiconductor 908e622 functional device operation operational modes a0 input and an alog multiplexer a0 - analog input input a0 is an analog input used for reading switches or as analog inputs for potentiometers, ntc, etc. a0 is internally connected to the analog multiplexer. this terminal offers a switchable current source. to read the analog input the terminal has to be selected with the ss[3:0] bits in the a0muctl register. figure 17. analog input and multiplexer a0 current source the terminal a0 provides a sw itchable current source, to be able to read in switches, nt c, etc. without the need of an additional supply line for the sensor. the overall enable of this feature is done by setting the pson bit in the system control register. in addition the terminal has to be selected with the ss[3:0] bits. the curr ent source can be enabled with bit cson and adjusted with the bits cssel[1:0]. with the cssel[1:0] bit?s four different current values can be selected (40, 120, 320 and 800a). this function is ceased during stop and sleep mode operation. the current source is derive d from the vdd voltage and is constant up to an output voltage of ~4.75v. to calibrate the current sources an extra terminal (a0cst) is foreseen. on this terminal an accurate resistor can to be connected. switching the current sources to this resistor allows the user to measure the current and use the measured value for calculating the current on a0. analog multiplexer / adout terminal the adout terminal is the analog output interface to the analog-to-digital converter of the mcu. to be able to have different sources for the mcu with one single signal an analog multiplexer adout 1% pson cson cssel ssx 4 source selection bits vdd a0cst analog port a0/a0cst selectable current source a0 ss[0:3] i a0 (u a0 ) u a0 [v] 5 4.75 100%
analog integrated circuit device data freescale semiconductor 33 908e622 functional device operation operational modes analog multiplexer is integrated in the analog die. this multiplexer has twelve different sources, which can be selected with the ss[3:0] bi ts in the a0muctl register. half-bridge (hb1:hb4) current recopy the multiplexer is connected to the four current sense circuits on the low side fet of the half bridges. this sense circuits offers a voltage propor tional to the current through the mosfet. the resolution is depending on bit csa in the a0 and multiplexer contro l register (a0muctl). high-side (hs1:hs3 ) current recopy the multiplexer is connected to the three high-side switches. this sense circuits offers a voltage proportional to the current through the transistor. analog input a0 and a0cst a0 and a0cst are directly connected to the analog multiplexer. it offers the possibili ty to read analog values from the periphery. temperature sensor the analog die includes an on chip temperature sensor. this sensor offers a voltage which is proportional to the actual mean chip junction temperature. vsup prescaler the vsup prescaler offers a possibility to measure the external supply voltage. the out put of this voltage is vsup / ratio vsup . ec output the ec output is directly connected to the multiplexer to be able to read the actual voltage on the ec terminal. a0 and multiplexer control register (a0muctl) cson ? current source on/off this read/write bit enables the current source for the a0 or a0cst inputs reset clears cson bit. 1 = current source enabled 0 = current source disabled cssel[1:0] ? current source select bits these read/write bits select the current source values for a0 or a0cst input. reset clears cssel[1:0] bits. table 7. a0 current source level selection bits csa ? h-bridges current sen se amplification select bit this read/write bit selects th e current sense amplification of the h-bridges hb1:hb4 current recopy. reset clears the csa bit. 1 = low current sense amplification 0 = high current sense amplification ss[3:0] ? analog source input select bits these read/write bits selects the analog input source for the adout terminal. reset clears the ss[3:0] bits table 8. analog multiplexer configuration bits. register name and address: a0muctl - $08 bit7 6 5 4 3 2 1 bit0 read cson cssel 1 cssel 0 csa ss3 ss2 ss1 ss0 write reset 0 0 0 0 0 0 0 0 cssel1 cssel0 current source enable (typ.) 0 0 40a 0 1 120a 1 0 320a 1 1 800a ss3 ss2 ss1 ss0 channel 0000 current recopy hb1 0001 current recopy hb2 0010 current recopy hb3 0011 current recopy hb4 0100 current recopy hs1 0101 current recopy hs2 0110 current recopy hs3 0111 not used 1000 chip temperature 1001 vsup prescaler 1010 terminal a0 1011 terminal a0cst 1100 terminal ec 1101 not used 1110 not used 1111 not used
analog integrated circuit device data 34 freescale semiconductor 908e622 functional device operation operational modes hall-effect sensor input terminal h0 the h0 terminal can be configured as general purpose input (h0ms = 0) or as hall-effect sensor input (h0ms = 1) to be able to read 3pin / 2pin hall sensors or switches. figure 18. general purpose / hall-effect sensor input (h0) current coded hallsensor input h0 is selected as ?2 pin hallsensor input?, if the corresponding h0ms bit in the h0/l0 status and control register (hlsctl) is set. in this mode the terminal current to gnd is monitored by a special sense circuitry. setting bit h0en in the h0/l0 status and control register switches the output to vsup and enable the sense circuitry. the result of the sense operation is given by the h0f flag. the flag is low if the sensed current is higher than the sense current threshold i hsct . in this configuration the ho terminal is protected (current limitation) against short circuit to gnd. after switching on the hallport (h0en = ?1?) the hallsensor needs some time to stabilize the output. in run mode the software has to take care ab out waiting for a few s (40) before sensing the hallflags. the hallport output current is sensed. in case of an overcurrent (short to gnd) th e hallport overcurrent flag (h0ocf) is set and the current is limited. for proper operation of the current limitation an external capacitor (>100nf) close to the h0 terminal is required. current sense h0en vsup h0en h0f h0ms h0ms vdd 10k h0 h0pd
analog integrated circuit device data freescale semiconductor 35 908e622 functional device operation operational modes figure 19. h0 used as 2-pin hallsensor input general purpose input h0 is selected as general purpose input, if the h0ms bit in the h0/l0 status and control re gister (hlsctl) is cleared. in this mode the input is usable as standard 5v input. the h0 input has a selectable internal pull-up resistors. the pull-up can be switched off with the h0pd bit in the h0/l0 status and control register (hlsctl). after reset the internal pull-up is enabled. figure 20. h0 used as 3 pin hall-effect sensor input current sense h0en vsup v h0f 2 pin hall sensor gnd h0 >0.1uf 3 pin hall sensor hvddon vdd h0pd vdd 10k h0f h0 hvdd gnd out vs gnd
analog integrated circuit device data 36 freescale semiconductor 908e622 functional device operation operational modes figure 21. h0 used to read in standard switches h0 interrupt the interrupt functionality on this terminal is just available in run mode. h0 interrupt flag h0if is set in run mode by a state change of the h0 flag (rising or falling edge on the enabled input). the interrupt func tion is available if the input is selected as general purpose or as 2pin hallsensor input. the interrupt can be masked with the h0ie bit in the interrupt mask register. wake-up input l0 the device provides one wake-up capable input for reading vsup or vdd related signals. run mode the actual input state is refl ected in bit l0f of the h0/l0 status and control register (hlsctl). the l0 terminal offers an interrupt capability on rising and falling edge. the interrupt can be enabled with the l0ie bit in the interrupt mask register. stop/sleep mode during stop and sleep mode the terminal can be used to wake-up the device. before entering the stop or sleep mode the actual state of the input is stored. if the st ate is changing during in the stop or sleep mode a wake-up is initiated. h0 / l0 status and control register (hlsctl) l0f ? l0 flag bit this read only flag reflects the state of the l0 input 1 = l0 input high 0 = l0 input low h0ocf ? h0 overcurrent flag bit this read/write flag is set at overcurrent condition on h0 during 2pin hallsensor mode. clear h0ocf by writing a logic [1] to h0ocf. reset clears the h0ocf bit. 1 = overcurrent condition on h0 terminal has occurred 0 = no overcurrent condition on h0 terminal has occurred h0f ? h0 flag bit this read only flag reflects the state of the h0 input 1 = hallport sensed high / current below threshold detected h0 gnd h0pd vdd 10k h0f register name and address: hlsctl - $07 bit7 6 5 4 3 2 1 bit0 read l0f 0 0 h0ocf h0f h0en h0pd h0ms write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data freescale semiconductor 37 908e622 functional device operation operational modes 0 = hallport sensed low / current above threshold detected h0en ? h0 input 2pin hall-effect sensor enable bit this read/write bit enables the 2pin hall-effect sensor sense circuitry. reset clears h0en bit. 1 = hallport h0 is switched on and sensed 0 = hallport h0 disabled h0pd ? hallport pull-up disable bit this read/write bit disables the h0 pull-up resistor. reset clears h0pd bit. 1 = hallport pull-up resistor on h0 disabled 0 = hallport pull-up resistor on h0 enabled h0ms ? h0 mode select these read/write bits select the mode of the h0 input reset clears h0ms bit. 1 = h0 is 2-pin hallsensor input 0 = h0 is general purpose input half-bridge outputs outputs hb1:hb4 provide four low-resistive half-bridge output stages. the half-bridges can be used in h-bridge, high-side or low-side configurations. reset clears all bits in the h-bridge output register (hbout) owing to the fact that all half-bridge outputs are switched off. hb1:hb4 output features ? short circuit (overcurrent) protection on high-side and low-side mosfets ? current recopy feat ure (low-side mosfet) ? overtemperature protection ? overvoltage and undervoltage protection ? active clamp on low-side mosfet figure 22. half-bridge push-pull output driver high-side driver charge pump overtemperature protection overcurrent protection low-side driver current recopy current limitation active clamp overcurrent protection control on/off status on/off status pwm hbx vsup gnd pwm
analog integrated circuit device data 38 freescale semiconductor 908e622 functional device operation operational modes half-bridge control each output mosfet can be controlled individually. the general enable of the circuitry is done by setting pson in the system control register (sysctl). the hbx_l and hbx_h bits form one half bridge. it is not possible to switch on both mosfets in one half-bridge at the same time. if both bits are set, the high-side mosfet is in pwm mode. to avoid both mosfets (high-side and low-side) of one half-bridge being on at the same time, a break-before-make circuit exists. switching the high-side mosfet on is inhibited as long as the potential between gate and v ss is not below a certain threshold. switching the low-side mosfet on is blocked as long as the potential between gate and source of the high-side mosfet did not fall below a certain threshold. half-bridge output register (hbout) hbx_h, hbx_l ? half br idge output switches these read/write bits select the output of each half-bridge output according to the following table. reset clears all hbx_h, hbx_l bits. table 9. half-bridge configuration half-bridge pwm mode the pwm mode is selected by setting both hbxl and hbxh of one half-bridge to ?1?. in this mode the high-side mosfet is controlled by the incoming pwm signal on the pwm terminal (see figure 2 , page 2 ). if the incoming signal is high, the high-side mosfet is switched on. if the incoming signal is low, the high-side mosfet is switched off. with the current recirculation mode control bit crm in the half-bridge status and control register (hbsctl) the recirculation behavior in pwm mode can be controlled. if crm is set the corresponding low-side mosfet is switched on if the pwm controlled high-side mosfet is off. half-bridge current recopy each low-side mosfet has an additional sense output to allow a current recopy featur e. these sense sources are internally amplified and switched to the analog multiplexer. the factor for the current sense amplification can be selected via bit csa in the a0muctl register (see page 32 ) csa = ?1?: low resolution selected csa = ?0?: high resolution selected half-bridge overtemperature protection the outputs are protected against overtemperature conditions. each power output comprises two different temperature thresholds. the first threshold is the high temperature interrupt (hti). if the temperature reaches this threshold the htif bit in the interrupt flag register (ifr) is set and an interrupt will be initiated if htie bit in the inte rrupt mask register is set. in addition this interrupt can be used to automatically turn off the power stages. this shutdown can be enabled/disabled by bits htis0-1 in the system control register (sysctl). the high temperature interrupts flag (htif) is cleared (and the outputs reenabled) by writing a ?1? to the htif flag in the interrupt flag register (ifr) or by a reset. clearing this flag has no effect as long as a high temperature condition is present. if the hti shutdown is disabled, a second threshold high temperature reset (htr) will be used to turn off all power stages (hb (all fet?s), hs, hvdd, ec, h0) in order to protect the device. half-bridge overcurrent protection the half-bridges are protec ted against short to gnd, vsup and load shorts. the overcurrent protection is implemented on each hb. if a overcurrent condition on the high-side mosfet occurs the high-side mosfet is automatically switched off. an overcurrent condition on the low-side mosfet will automatically turn off the low-side mosfet. in both cases the co rresponding hbxocf flag in the half-bridge status and cont rol register (hbsctl) is set. the overcurrent status flag is cleared (and the corresponding half-bridge mosfets reenabled) by writing a ?1? to the hbxocf in the half-bridge status and control register (hbsctl) or by a reset. register name and address: hbout - $01 bit7 6 5 4 3 2 1 bit0 read hb4_h hb4_l hb3_h hb3_l hb2_h hb2_l hb1_h hb1_l write reset 0 0 0 0 0 0 0 0 hbx_h hbx_l mode 0 0 low-side and high-side mosfet off 0 1 high-side mosfet off, low-side mosfet on 1 0 high-side mosfet on, low-side mosfet off 1 1 high-side mosfet in pwm mode
analog integrated circuit device data freescale semiconductor 39 908e622 functional device operation operational modes half-bridge overvoltage/undervoltage protection the half-bridge outputs are protected against undervoltage and overvoltage conditions. this protection is done by the low and high voltage in terrupt circuitry. if one of this flags (lvif, hvif) is se t, the outputs ar e automatically disabled if the vis bit in the system control register (sysctl) is cleared. the overvoltage and undervoltage status flags are cleared (and the outputs reenabled) by wr iting a ?1? to the lvif / hvif flags in the interrupt flag register (ifr) or by a reset. clearing this flag has no effect as long as the high voltage or low voltage condition is still present. half-bridge status and control register (hbsctl) crm ? current recirc ulation mode bit this read/write bit selects the recirculation mode during pwm. reset clears the crm bit. 1 = recirculation via switched on low-side mosfet 0 = recirculation via low-side free wheeling diode hbxocf ? half bridges overcurrent flag bit this read/write bit indicates that an overcurrent condition on either the ls or the hs fet on hbx has occurred. clear hbxocf and enable half bridge by writing a logic [1] to hbxocf. writing a logic [0] to hbxocf has no effect. reset clears the hbxocf bit. 1 = overcurrent condition on hbx occurred 0 = no overcurrent condition on hbx high-side drivers the high-side outputs are low resistive high-side switches, targeted for driving lamps. the high-sides are protected against overtemperature, ov ercurrent and overvoltage/ undervoltage. figure 23. hs circuitry high-side operating modes the high-sides outputs are enabled if the pson bit in the system control register (sysctl) is set. each high-side output is perm anently switched on, if the hsxon bit in the high-side outp ut register (hsout) is set. pwm control of the output is enabled, if the hsxpwm bit high-side output register (hso ut) is set. in this operating mode the high-side mosfet is on, if the input pwm signal (pwm terminal) is high. the below table shows the behavior of the high-side mosfets depending on the hsonx and pwmhsx bits. register name and address: hbsctl - $03 bit7 6 5 4 3 2 1 bit0 read crm 0 0 0 hb4 ocf hb3 ocf hb2 ocf hb1 ocf write reset 0 0 0 0 0 0 0 0 vsup hsx hs - driver charge pump over-current protection inrush current limiter pwm control on/off current limit status pson hsxon hsxpwm pwm
analog integrated circuit device data 40 freescale semiconductor 908e622 functional device operation operational modes table 10. high-side configuration bits high-side overvoltage / undervoltage protection the outputs are prot ected against under- / overvoltage conditions. this protection is done by the low and high voltage interrupt circuitry. if an over- under voltage condition is detected (lvif / hvif) and bi t vis in the high-side status register is cleared, the output is disabled. the over- / undervoltage status flags are cleared (and the output reenabled) by writing a logic [1] to the lvif / hvif flags in the interrupt flag register or by reset. clearing this flag has no effect as long as a high or low voltage condition is present. high-side overtemperature protection the outputs are protected against over temperature conditions. each power output comprises two different temperature thresholds. the first threshold is the high temperature interrupt (hti), if the temperature reach this threshold the hti bit in the interrupt flag register is set and an interrupt will be generated if htie bit in the interrupt mask register is set. in addition this interrupt can be used to automatically turn off the power stages (all high-sides, on half bridges just the high-side fet?s). this shutdown can be enabled/disabled by bit htis0. the high temperature interrupts flag (htie) is cleared (and the outputs reenabled) by writing a logic [1] to the htif flag in the interrupt status register or by reset. clearing this flag has no effect as long as a high temperature condition is present. if the htis shutdown is disabled, a second threshold (htr) will be used to turn off all power stages (hb (all fet?s), hs, hvdd, ec, h0) in order to protect the device. high-side overcurrent protection the hs outputs are protecte d against overcurrent. when the overcurrent limit is reached, the output will be automatically switched off and the overcurrent flag is set. due to the high inrush current of bulbs a special feature was implemented to avoid a over current shutdown during this inrush current. if a pwm frequency will be supplied to the pwm input during the switch on of a bulb, the inrush current will be limited to the overcurrent shutdown limit. this means, if the current reaches the ov ercurrent shutdown, the high- side will be switched off, but each rising edge on the pwm input will enable the dr iver again. the duty cycle supplied by the mcu has no influence on t he switch-on time of the high- side driver. in order to distinguish between a shutdown due to an inrush current or a real shutdown, the software has to check if the overcurrent status fl ag (hsxocf) in the high-side status register is set beyond a certain period of time. hsxpwm hsxon mode 0 0 high-side mosfet off 0 1 high-side mosfet on, in case of overcurrent the overcurrent flag (hsxocf) is set and the high-side mosfet is turned off 1 0 in this mode the pwm duty cycle is either controlled by the pwm input signal or in case the overcurrent shutdown value is reached by the part itself. without reaching the overcurrent shutdown, the high-side driver is directly driven from the pwm input signal. if the input signal is high the output is on, if low the output is off (pwm control). if the current reaches the overcurrent shutdown value, the high-side will be automatically turned off, with the next rising edge of the pwm input signal the output will turn on again (current limitation). the hsxocf bit will be set, software has to distinguish between an inrush current and a real short on the output. 1 1 high-side mosfet is switched on and the inrush current limitation is enabled, means the high side will start automatically with an current limitation around the overcurrent shutdown threshold. (pwm signal must be applied, see figure 24 ) if the high-side enters current limitation the hsxocf bit is set, but the output is not disabled. the software needs to take care about distinguish between an inrush current and a real short on the output.
analog integrated circuit device data freescale semiconductor 41 908e622 functional device operation operational modes figure 24. inrush current limitation on hs outputs high-side current recopy each high-side has an additional sense output to allow a current recopy feature. this sense source is internally connected to a shunt resistor. the drop voltage is amplified and switched to the analog multiplexer. switchable hvdd outputs the hvdd terminal is a switchable 5v output terminal. it can be used for driving external circuitry which requires a 5v voltage. the output is enabled with bit pson in the system control register and can be switched on / off with bit hvdd_on in the high-side out register. low or high voltage conditions (lvif / hvif) will have no influence on this circuitry. hvdd over temperature protection the output is protected against over temperature conditions. hvdd over current protection the hvdd output is protected against overcurrent. in case the current reach the overcurrent limit, the output current will be limited and the hvddocf overcurrent flag in the system status register is set. high-side out register (hsout) hvdd-on ? hvdd on bit this read/write bit ena bles the hvdd output. reset clears hvddon bit. 1 = hvdd enabled 0 = hvdd disabled hsxon ? high-side on/off bits these read/write bits turn on the high-side fet?s permanently reset clears the hsxon bits. 1 = high-side x is turned on 0 = high-side x is turned off hs current hs over-current shutdown threshold pwm terminal t t register name and address: hsout - $02 bit7 6 5 4 3 2 1 bit0 read hvdd on 0 hs3p wm hs2p wm hs1p wm hs3o n hs2o n hs1o n write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data 42 freescale semiconductor 908e622 functional device operation operational modes hsxpwm ? high-side pwm on/off bits these read/write bits enable the pwm control of the high- side fet?s. reset clears the hsxpwm bits. 1 = high-side x is controlled by pwm input signal 0 = high-side x is not controlled by pwm input signal high-side status register (hsstat) hsxocf ? high-side overcurrent flag bit this read/write flag is set by an overcurrent condition at the high-side drivers x. clear hsxocf and enable the hs driver by writing a logic [1] to hsxocf. writing a logic [0] to hsxocf has no effect. reset clears the hsxocf bit. 1 = overcurrent condition on high-side drivers has occurred 0 = no overcurrent condition on high-side drivers has occurred hvddocf ? hvdd output overcurrent flag bit this read/write flag is set by an overcurrent condition at hvdd terminal. clear hvddocf and enable the output by writing a logic [1] to the hvddocf flag. writing a logic [0] to hvddocf has no effect. reset clears the hvddocf bit. 1 = overcurrent condition on vdd output has occurred 0 = no overcurrent condition on vdd output has occurred register name and address: hsstat - $04 bit7 6 5 4 3 2 1 bit0 read hvdd ocf 0 0 0 0 hs3o cf hs2o cf hs1o cf write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data freescale semiconductor 43 908e622 functional device operation operational modes electrochrome circuitry the ec glass is controlled by two transistors. t1 is switching on/off the ec glass and t2 is controlling the ec output voltage given by the 6bit da converter. figure 25. ec circuitry ec open load detection open load can be detected by setting ecolt. a small current source is sourcing a current of typical 200ua on the ec terminal and the voltage on the terminal is measured. in case the voltage is above typical 2v (typical 10k threshold) the ecolf bit in the ec status and control register ecsctl is set indicating the open load condition. if the open load circuitry is activated (ecolt=1) the ec glass is disabled. ec short circuit protection the ec output is protected against shorts to vsup. in case of an short circuit the ecocf in the ec status and control register (ecsctl) is set and the ec circuitry is disabled. the ec output is protected agai nst shorts to gnd. in case of an short circuit the ecocf in the ec status and control register (ecsctl) is set and the ec circuitry is disabled. ec digital to analog converter the ec output and therefore the voltage on the ec glass is controlled. the ec glass circuitry has a 6 bit d/a converter to control the output voltage between 0 and 1,4v. ec d/a converter control register (ecdacc) ecdax ? digital to analog bits these read/write bits set the output voltage on the ec terminal. vsup ecr ec gnd control ec output voltage ecocf ecol ecocf on/off t1 t2 6bit dac econ ecron on/off register name and address: ecdacc - $06 bit7 6 5 4 3 2 1 bit0 read 0 0 ecda5 ecda4 ecda3 ecda2 ecda1 ecda0 write reset 0 0 0 0 0 0 0 0
analog integrated circuit device data 44 freescale semiconductor 908e622 functional device operation operational modes ec status and control register (ecsctl) econ ? electrochrome circuitry enable bit this read/write bit enable s transistor t2 of the electrochrome circuitry. reset clears the econ bit. 1 = t2 ec circuitry enabled 0 = t2 ec circuitry disabled ecolt ? electrochrome circuitry open load test bit this read/write bit enables the open load test for the electrochrome circuitry. if this bit is set the ec glass functionality is ceased. reset clears the ecolt bit. 1 = ec open load circuitry enabled 0 = ec open load circuitry disabled ecron ? ec resistor enable bit this read/write bit enable s transistor t1 of the electrochrome circuitry. reset clears the ecron bit. 1 = t1 ec circuitry enabled 0 = t1 ec circuitry disabled note: controlling the output voltage on terminal ec is done by transistor t2 only. the enable of t1 will switch the vsup voltage via the external ec resistor to the ec glass. ecocf ? ec output overcurrent flag bit this read/write flag is set on short circuit condition at the ec output (short to vsup/ short to gnd). clear ecocf and enable the ec circuitry by writing a logic [1] to ecocf. writing a logic [0] to ecocf has no effect. reset clears the ecocf bit. 1 = short circuit condition on ec output detected 0 = no short circuit condition on ec output detected ecolf ? ec open load flag bit this read/write flag is set on an open load condition of the ec output. clear ecolf and disable the ec circuitry by writing a logic [1] to ecolf. writing a logic [0] to ecolf has no effect. reset clears the ecolf bit. 1 = open load condition on ec output detected 0 = no open load condition on ec output detected system control register (sysctl) pson ? power stages on bit this read/write bit enables the power stages (half bridges, high-sides, lin transmitter, a0 current sources and hvdd output). reset clears the pson bit. 1 = power stages enabled 0 = power stages disabled stop ? change to stop mode bit this write bit instructs the chip to enter stop mode ( see operational modes on page 24 ). reset or cpu interrupt requests clear the stop bit. 1 = go to stop mode 0 = not in stop mode in order to safely stop mode all other bits (bit7-bit2) have to be ?0?. otherwise the stop command will not be executed. sleep ? change to sleep mode bit this write bit instructs the chip to enter sleep mode ( see operational modes on page 24 ). reset or cpu interrupt requests clear the sleep bit. 1 = go to sleep mode 0 = not in sleep mode in order to safely enter sleep mode all other bits (bit7-bit2) have to be ?0?. otherwise the sleep command will not be executed. htis0-1 ? high temperature interrupt shutdown bits this read/write bits selects the power stage behavior at high temperature interrupt (hti). reset clears the htis0-1 bits. the htis0 bit selects the behavior of the high-side hs1:3 and the high-side fet of the half-bridges hb1:4. 1 = automatic hti shutdown of the high-side drivers disabled 0 = automatic hti shutdown of the high-side drivers enabled the htis1 bit selects the behavior of the low-side drivers of the half-bridges hb1:4. 1 = automatic hti shutdown of the low-side drivers disabled register name and address: ecsctl - $05 bit7 6 5 4 3 2 1 bit0 read econ ecolt ecron 0 0 0 ecoc f ecolf write reset 0 0 0 0 0 0 0 0 register name and address: sysctl - $00 bit7 6 5 4 3 2 1 bit0 read pson 00 htis1 htis0 vis srs1 srs0 write stop sleep reset 0 0 0 0 0 0 0 0
analog integrated circuit device data freescale semiconductor 45 908e622 functional device operation operational modes 0 = automatic hti shutdown of the low-side drivers enabled the user has to take care to protect the device against thermal destruction! vis ? over-/undervoltage interrupt shutdown this read/write bit selects the power stage behavior at lvi/ hvi. reset clears the vis bit. 1 = automatic lvi/hvi shutdown disabled 0 = automatic lvi/hvi shutdown enabled srs0-1 ? lin slew rate select bits these read/write bits enable the user to select the appropriate lin slew rate for different baudrate configurations. reset clears the srs1:0 bits. table 11. lin slew rate selection bits the high speed slew rates are used, for example, for programming via the lin and are not intended for use in the application. system status register (sysstat) lincl ? lin current limitation bit this read only bit is set if the lin transmitter operates in current limitation region. due to excessive power dissipation in the transmitter, the driver will be automatically turned off after a certain time. 1 = transmitter operating in current limitation region 0 = transmitter not operating in current limitation region htif? overtemperature status bit this read only bit is a copy of the htif bit in the interrupt flag register 1 = overtemperature condition 0 = no overtemperature condition vf ? voltage failure bit this read only bit indicates that the supply voltage was out of the allowed range. the bit is set if either the lvif or the hvif in the interrupt flag register is set. 1 = low/high voltage condition detected 0 = no voltage failure condition detected figure 26. vf flag generation h0f ? h0 failure bit this read only bit is a copy of the h0ocf bit in the h0/l0 status and control register (hlsctl) 1 = overcurrent detected on h0 0 = no overcurrent on h0 hvddf? hvdd failure bit this read only bit is a copy of the hvddocf bit in the high-side status register 1 = hvdd terminal fail 0 = hvdd normal operating hsf? hs1:3 failure bit this read only bit is set if a fail condition on one of the high- side outputs is present 1 = hs1:3 terminal fail 0 = hs1:3 normal operating figure 27. hsf flag generation hbf? hb1:4 failure bit this read only bit is set if a fail condition on one of the half bridge outputs is present. 1 = hb1:4 terminal overcurrent fail 0 = hb1:4 normal operating figure 28. hbf flag generation srs1 srs0 slew rate 0 0 initial slew rate (20kbaud) 0 1 high speed ii (8x) 1 0 slow slew rate (10kbaud) 1 1 high speed i (4x) register name and address: sysstat - $0c bit7 6 5 4 3 2 1 bit0 read linc l htif vf h0f hvd df hsf hbf ecf write reset 0 0 0 0 0 0 0 0 lvif hvif vf hs3ocf hs2ocf hs1ocf hsf hb1ocf hb2ocf hb3ocf hb4ocf hbf
analog integrated circuit device data 46 freescale semiconductor 908e622 functional device operation operational modes ecf? ec terminal failure bit this read only bit is set if a fail condition on the electrochrome output is present 1 = ec terminal fail 0 = ec normal operating figure 29. ecf flag generation window watchdog the window watchdog is to supervise the device and to recover from e.g. code runaways or similar conditions. the use of a window watchdog adds additional safety as the watchdog clear has not only to occur but to be done at a certain time frame / window. normal mode the window watchdog function is just available in normal mode and is ceased in stop and sleep mode. on setting the wdre bit, the watchdog functionality is activated. once this function is enabled it is not possible to disable it via software. reset clears the wdre bit. to prevent a watchdog reset, the watchdog timer has to be cleared in the window open fr ame. this is done by writing a logic ?1? to the wdrst bit in the watchdog control register (wdctl). the actual reset of the watchdog counter occurs at the end of the corresponding spi transmission with the rising edge of the ss signal. if the watchdog is enabled, it will generate a system reset if the timer has reached its end value or if a watchdog reset (wdrst) has occurred in the closed window. the watchdog period can be selected with 2 bits in the wdctl, in order to get 10m s, 20ms, 40ms and 80ms period. figure 30. window watchdog period stop mode operations of the watchdog function is ceased in stop mode (counter/oscillator st opped). after wake-up the watchdog timer is automatically cleared in order to give the mcu the full time to reset the watchdog. sleep mode operations of the watchdog function is ceased is sleep mode. due to the reason that the main voltage regulator asserts an lvr reset the watchdog functionality is disabled and the wdre bit is cleared as soon as sleep mode is entered. to reenable this function bit wdre has to be set after wake-up. watchdog control register (wdctl) wdre - watchdog reset enable bit this read/write (write once) bit activates the watchdog the wdre can only be set and can?t be cleared by software. reset clears the wdre bit. 1 = watchdog enabled 0 = watchdog disabled wdp1:0 - watchdog period select bits this read/write bit select the clock rate of the watchdog. reset clears the wdp1:0 bits. table 12. watchdog period selection bits wdrst - watchdog reset bit this write only bit resets the watchdog. write a logic [1] to reset the watchdog timer. 1 = reset wd and restart timer 0 = no effect ecocf ecolf ecf window closed no watch dog clear allowed window open for watch dog clear wd timing x 50% wd timing x 50% wd period ( timing selected by bits wdp1:0) register name and address: wdctl - $0b bit7 6 5 4 3 2 1 bit0 read wdre wdp1 wdp00000 0 write wdrst reset 0 0 0 0 0 0 0 0 wdp1 wdp0 mode 0 0 80ms window watchdog period 0 1 40ms window watchdog period 1 0 20ms window watchdog period 1 1 10ms window watchdog period
analog integrated circuit device data freescale semiconductor 47 908e622 functional device operation operational modes voltage regulator the 908e622 contains a low power, low drop voltage regulator to provide internal power and external power for the mcu. the on-chip regulator co nsist of two elements, the main regulator and the low voltage reset circuit. the v dd regulator accepts an unregulated input supply and provides a regulated v dd supply to all digital sections of the device. the output of the re gulator is also connected to the vdd terminal to provide the 5.0 v to the microcontroller. run mode during run mode the main voltage regulator is on. it will provide a regulated supply to all digital sections. stop mode during stop mode, the stop mode regulator will take care of suppling a regulated outp ut voltage. the stop mode regulator has a limited output current capability. sleep mode in sleep mode the main voltage regulator external v dd is turned off and the lvr circuitry will force the rst_a terminal low.
analog integrated circuit device data 48 freescale semiconductor 908e622 functional device operation logic commands and registers logic commands and registers 908e622 serial pheripheral interface (spi) the serial peripheral interface (spi) creates the communication link between the mcu and the analog die. the interface consists of four terminals ? mosi - master out slave in (internal pull-down) ? miso - master in slave out ? spsck - serial clock (internal pull-down) ?ss - slave select (internal pull-up) a complete data transfer via the spi, consists of 2 bytes. the master sends address and data, the slave returns system status and the data of the selected address. figure 31. spi protocol ? during the inactive phase of ss , the new data transfer will be prepared. the falling edge on the ss line, indicates the start of a new data transfer (framing) and puts miso in the low impedance mode. the first valid data are moved to miso wit h the rising edge of spsck. ? the mosi, miso will change data on a rising edge of spsck. ? the mosi, miso will be sampled on a falling edge of spsck. ? the data transfer is only valid, if exactly 16 sample clock edges are present in the active phase of ss. ? after a write operation the transmitted data will be latched into the register, by the rising edge of ss . ? register read data is inter nally latched into the spi, at the time when the parity bit is transferred ?ss high will force miso to high impedance master address byte a4 - a0 include the address of the desired register. r/w includes the information if it is a read or a write operation. ?if r/w = 1 (read operation), second byte of master contains no valid information, slave just transmits back register data. ?if r/w = 0 (write operation), master sends data to be written in the second byte , slave sends concurrently contents of selected register prior to write operation, write data is latched in the smartmos registers on rising edge of ss parity p completes the total number of 1 bits of (r/w,a[4-0]) to an even number. e.g. (r/w,a[4-0]) = 100001 -> p0 = 0. the parity bit is only evalua ted during a write operations and ignored for read operations. bit x not used s7 s6 s5 s4 s3 s2 s1 s0 r/w a4 a3 a2 a1 a0 p x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 system status register read/write, address, parity data (register write) data (register read) rising edge of spsck change miso/mosi output falling edge of spsck sample miso/mosi input slave latch register address slave latch data ss mosi miso spsck
analog integrated circuit device data freescale semiconductor 49 908e622 functional device operation logic commands and registers master data byte this byte includes data to be wr itten or no valid data during a read operation. slave status byte this byte include s always the contents of the system status register ($0c) independent if it is a write or read operation or which register was selected. slave data byte this byte includes the conten ts of selected register, during write operation in includes the register content prior to write operation.
analog integrated circuit device data 50 freescale semiconductor 908e622 functional device operation logic commands and registers spi register overview table 13 summarizes the spi register addresses and the bit names of each register. table 13. spi re gister overview addr register name r/w bit 76543210 $00 system control (sysctl) r pson 00 htis1 htis0 vis srs1 srs0 w stop sleep $01 half-bridge output (hbout) r hb4_h hb4_l hb3_h hb3_l hb2_h hb2_l hb1_h hb1_l w $02 high-side output (hsout) r hvddon 0 hs3pwm hs2pwm hs1pwm hs3on hs2on hs1on w $03 half-bridge status and control (hbsctl) r crm 00 0 hb4ocf hb3ocf hb2ocf hb1ocf w $04 high-side status and control (hssctl) r hvddocf 00 0 0 hs3ocf hs2ocf hs1ocf w $05 ec status and control (ecsctl) r econ ecolt ecron 000 ecocf ecolf w $06 ec digital to analog control (ecdacc) r 00 ecdac5 ecdac4 ecdac3 ecdac2 ecdac1 ecdac0 w $07 h0/l0 status and control (hlsctl) r l0f 0 0 h0ocf h0f h0en h0pd h0ms w $08 a0 and multiplexer control (a0muctl) r cson cssel1 cssel0 csa ss3 ss2 ss1 ss0 w $09 interrupt mask (imr) r l0ie h0ie linie htrd htie lvie hvie psfie w $0a interrupt flag (ifr) r l0if h0if linif 0 htif lvif hvif psfif w $0b watchdog control (wdctl) r wdre wdp1 wdp0 00000 w wdrst $0c system status (sysstat) r lincl htif vf h0f hvddf hsf hbf ecf w $0d reset status (rsr) r por pinr wdr htr lvr 0 linwf l0wf w $0e system test (systest) r reserved w $0f system trim 1 (systrim1) r hvddt1 hvddt0 reserved reserved itrim3 itrim2 itrim1 itrim0 w $10 system trim 2 (systrim2) r 00000000 w crhbhc1 crhbhc0 crhb5 crhb4 crhb3 crhb2 crhb1 crhb0 $11 system trim 3 (systrim3) r 00000000 w crhbhc3 crhbhc2 crhs5 crhs4 crhs3 crhs2 crhs1 crhs0
analog integrated circuit device data freescale semiconductor 51 908e622 functional device operation logic commands and registers factory trimming and calibration to enhance the ease-of-use of the 908e622, various parameters (e.g. icg trim value) are stored in the flash memory of the device. the following flash memory locations are reserved for this purpose and might have a value different from the ?empty ? ($ff) state: ? $fd80:$fddf trim and calibration values ? $fffe:$ffff reset vector in the event the application uses these parameters, one has to take care not to erase or override these values. if these parameters are not used, these flash locations can be erased and otherwise used. trim values below the usage of the trim values located in the flash memory is explained internal clock genera tor (icg) trim value the internal clock generator (icg) module is used to create a stable clock source for the microcontroller without using any external components. the untrimmed frequency of the low frequency base clock (ibase), will vary as much as 25 percent due to process, temperature, and voltage dependencies. to compensate this dependencies a icg trim values is located at address $fdc2. after trimming the icg is a range of typ. 2% (3% max.) at nominal conditions (filtered (100nf) and stabilized (4,7uf) v dd = 5v, t ambient ~25c) and will vary over temperature and voltage (v dd ) as indicated in t he 68hc908ey16 datasheet. to trim the icg this values has to be copied to the icg trim register icgtr at address $38 of the mcu. important the value has to copied after every reset. watchdog period range value (awd trim) the window watchdog supervises device recover from e.g. code runaways. the application software has to clear the watchdog within the open window. due to the hi gh variation of the watchdog period - and therefore the redu ced width of the watchdog window - a value is stored at address $fdcf. this value classifies the watchdog period into 3 ranges (range 0, 1, 2). this allows the application software to select one out of three time intervals to clear the watchdog based on the stored value. the classification is done in a way that the application software can have up to 19% va riation of the of optimal clear interval, e.g. caused by icg variation. effective open window having a variation in the watchdog period in conjunction with a 50% open window results in effective open window, which can be calculated by: latest window open time: t_open = t_wd max / 2 earliest window closed time: t_closed = t_wd min optimal clear interval the optimal clear interval - meaning the clear interval with the biggest possible variation to latest window open time and to the earliest window closed ti me can be calculated with the following formula: t_opt = t_open + (t_ open+t_closed) / 2 see table 14 to select the optimal clear interval for the watchdog based on the window no. and chosen period. table 14. window clear interval window range period select bits watchdog period t_wd effective open window optimal clear interval $fdcf wdp1:0 min. max. unit t_open t_closed unit t_opt unit max. variation 0 00 68 92 ms 46 68 ms 57 ms 19.3% 01 34 46 23 34 28.5 10 17 23 11.5 17 14.25 11 8.5 11.5 5.75 8.5 7.125 1 00 92 124 ms 62 92 ms 77 ms 19.5% 01 46 62 31 46 38.5 10 23 31 15.5 23 19.25 11 11.5 15.5 7.75 11.5 9.625 2 00 52 68 ms 34 52 ms 43 ms 20.9% 01 26 34 17 26 21.5 10 13 17 8.5 13 10.75 11 6.5 8.5 4.25 6.5 5.375
analog integrated circuit device data 52 freescale semiconductor 908e622 functional device operation logic commands and registers analog die system trim values for improved application perfor mance and to ensure the outlined datasheet values the analog die needs to be trimmed. for this purpose 3 trim values are stored in the flash memory at address $fdc4 - $fdc6. these values have to be copied into the analog die spi registers: ? copy $fdc4 into systrim1 register $0f ? copy $fdc5 into systrim2 register $10 ? copy $fdc6 into systrim3 register $11 note: this values have to be copied to the respective spi register after a reset to ensure proper trimming of the device. system test register (systest) the system test register is reserved for production testing and is not allowed to be written to. system trim register 1 (systrim1) hvddt1:0 - hvdd overcurre nt shutdown delay bits these read/write bits allow to change the filter time (for capacitive load) for the hvdd over current detection. reset clears the hvddt1:0 bits an sets the delay to the maximum value. table 15. hvdd overcurrent shutdown selection bits itrim3:0 - iref trim bits these write only bits are for trimming of the internal current references iref (also a0, a0cst). the provided trim values have to be copied into these bits after every reset. reset clears the itrim3:0 bits. table 16. iref trim bits system trim register 2 (systrim2) crhbhc1:0 - current recopy hb1:2 trim bits these write only bits are for trimming of the current recopy of the half-bridge hb1 and hb2 (csa=0). the provided trim values have to be copied into these bits after every reset. reset clears the crhbhc1:0 bits. table 17. current recopy trim for hb1:2 (csa=0) register name and address: systest - $0e bit7 6 5 4 3 2 1 bit0 read reserved reserved reserved reserved reserved reserved reserved reserved write reset 0 0 0 0 0 0 0 0 note: do not write to the reserved bits register name and address: ibias - $0f bit7 6 5 4 3 2 1 bit0 read hvddt1 hvddt0 0 reserved 0 reserved itrim3 itrim2 itrim1 itrim0 write reset 0 0 0 0 0 0 0 0 note: do not change (set) the reserved bits hvddt1 hvddt0 typical delay 0 0 950us 0 1 536us 1 0 234us 1 1 78us itrim3 itrim2 itrim2 itrim0 adjustment 0000 0 0001 2% 0010 4% 0011 8% 0100 12% 0101 -2% 0110 -4% 0111 -8% 1000 -12% register name and address: ifbhbtrim - $10 bit7 6 5 4 3 2 1 bit0 read 0 0 0 0 0 0 0 0 write crhbhc1 crhbhc0 crhb5 crhb4 crhb3 crhb2 crhb1 crhb0 reset 0 0 0 0 0 0 0 0 crhbhc1 crhbhc0 adjustment 00 0 01 -10% hvddt1 hvddt0 typical delay
analog integrated circuit device data freescale semiconductor 53 908e622 functional device operation logic commands and registers crhb5:3 - current recopy hb3:4 trim bits these write only bits are for trimming of the current recopy of the half-bridge hb3 and hb4 (csa=1). the provided trim values have to be copied into these bits after every reset. reset clears the crhb5:3 bits. table 18. current recopy trim for hb3:4 (csa=1) crhb2:0 - current recopy hb1:2 trim bits these write only bits are for trimming of the current recopy of the half-bridge hb1 and hb2 (csa=1). the provided trim values have to be copied into these bits after every reset. reset clears the crhb2:0 bits. table 19. current recopy trim for hb1:2 (csa=1) system trim register 3 (systrim3) crhbhc3:2 - current recopy hb3:4 trim bits these write only bits are for trimming of the current recopy of the half-bridge hb3 and hb4 (csa=0). the provided trim values have to be copied into these bits after every reset. reset clears the crhbhc3:2 bits. table 20. current recopy trim for hb3:4 (csa=0) crhs5:3 - current recopy hs2:3 trim bits these write only bits are for trimming of the current recopy of the high-side hs2 and hs3. the provided trim values have to be copied into these bits after every reset. reset clears the crhs5:3 bits. table 21. current recopy trim for hs2:3 10 5% 1 1 10% crhb5 crhb4 crhb3 adjustment 000 0 001 -5% 010 -10% 011 -15% 1 0 0 reserved 101 5% 110 10% 111 15% crhb2 crhb1 crhb0 adjustment 000 0 001 -5% 010 -10% 011 -15% 1 0 0 reserved 101 5% 110 10% 111 15% crhbhc1 crhbhc0 adjustment register name and address: ifbhstrim - $11 bit7 6 5 4 3 2 1 bit0 read 0 0 0 0 0 0 0 0 write crhbh c3 crhbh c2 crhs5 crhs4 crhs3 crhs2 crhs1 crhs0 reset 0 0 0 0 0 0 0 0 crhbhc3 crhbhc2 adjustment 00 0 01 -10% 10 5% 1 1 10% crhs5 crhs4 crhs3 adjustment 000 0 001 -5% 0 1 0 -10% 0 1 1 -15% 1 0 0 reserved 101 5% 110 10% 111 15%
analog integrated circuit device data 54 freescale semiconductor 908e622 functional device operation logic commands and registers crhs2:0 - current recopy hs1 trim bits these write only bits are for trimming of the current recopy of the high-side hs1. the provided trim values have to be copied into these bits after every reset. reset clears the crhs2:0 bits. current recopy trim for hs1 crhs2 crhs1 crhs0 adjustment 000 0 001 -5% 010 -10% 0 1 1 -15% 1 0 0 reserved 101 5% 110 10% 111 15% crhs2 crhs1 crhs0 adjustment
analog integrated circuit device data freescale semiconductor 55 908e622 typical applications typical applications development support as the 908e622 has the mc68hc908ey16 mcu embedded, typically all the development tools available for the mcu also apply for this device. however, due to the additional analog die circuitry and the nominal +12v supply voltage, some additional items have to be considered: ? nominal 12v rather than 5v or 3v supply ? high voltage v tst might be applied not only to irq terminal, but irq_a terminal ? mcu monitoring (normal request time-out) has to be disabled for a detailed information on the mcu related development support see the mc68hc908ey16 datasheet - section development support. the programming is principally possible at two stages in the manufacturing process - first on chip level, before the ic is soldered onto a pcb board, and second after the ic is soldered onto the pcb board. chip level programming at the chip level, the easiest way is to only power the mcu with +5v (see figure 32 ), and not to provide the analog chip with vsup. in this setup all the analog terminal should be left open (e.g. vsup[1:8]) and in terconnections between mcu and analog die have to be separated (e.g. irq - irq_a ). this mode is well described in the mc68hc908ey16 datasheet - section development support. figure 32. normal monito r mode circuit (mcu only) of course its also possible to supply the whole system with vsup instead (12v) as described in figure 33 , page 56 . MM908E622 rst_a rst irq_a irq vsup[1:8] gnd[1:4] ptc4/osc1 ptb3/ad3 ptb4/ad4 pta0/kbd0 pta1/kbd1 testmode max232 10k rs232 db-9 1 3 c1+ c1- 4 5 c2+ c2- 7 8 2 3 5 v cc gnd 16 15 2 v+ v- 6 1f + 1f + + 1f 1f + + 1f 2 1 3 65 4 74hc125 74hc125 9.8304mhz clock +5v +5v data clk +5v 10k 10k 10k v tst 10 9 t2 out r2 in t2 in r2 out vssa/vrefl vdda/vrefh evdd vdd evss vss 4.7f 100nf +5v
analog integrated circuit device data 56 freescale semiconductor 908e622 typical applications pcb level programming if the ic is soldered onto t he pcb board, its typically not possible to separately power the mcu with +5v. the whole system has to be powered up providing v sup (see figure 33 ).. figure 33. normal monitor mode circuit table 22 summarizes the possible configurations and the necessary setups. MM908E622 rst_a rst irq_a irq vssa/vrefl vdda/vrefh evdd vdd evss vss vsup[1:8] gnd[1:4] 4.7f 100nf ptc4/osc1 ptb3/ad3 ptb4/ad4 pta0/kbd0 pta1/kbd1 testmode max232 10k rs232 db-9 1 3 c1+ c1- 4 5 c2+ c2- 7 8 2 3 5 v cc gnd 16 15 2 v+ v- 6 1f + 1f + + 1f 1f + + 1f 2 1 3 65 4 74hc125 74hc125 9.8304mhz clock v dd v dd data clk v dd 10k 10k 10k 10k v dd v tst v sup 47f + 100nf 10 9 t2 out r2 in t2 in r2 out table 22. monitor mode signal requirements and options mode irq rst testmode reset vector serial communication mode selection icg cop normal request time-out communication speed pta0 pta1 ptb3 ptb4 external clock bus frequency baud rate normal monitor v tst v dd 1 x 1 0 0 1 off disabled disabled 9.8304 mhz 2.4576 mhz 9600 forced monitor v dd v dd 1 $ffff (blank) 10xx off disabled disabled 9.8304 mhz 2.4576 mhz 9600 gnd on disabled disabled ? nominal 1.6mhz nominal 6300 user v dd v dd 0 not $ffff (not blank) x x x x on enabled enabled ? nominal 1.6mhz nominal 6300 notes 1. pta0 must have a pullup resistor to v dd in monitor mode 2. external clock is a 4.9152mhz, 9.8304mhz or 19.6608mhz canned oscillator on ocs1 3. communication speed with external clock is depending on external clock value. baud rate is bus frequency / 256 4. x = don?t care 5. v tst is a high voltage v dd +3.5v v tst v dd +4.5v
analog integrated circuit device data freescale semiconductor 57 908e622 typical applications emc/emi recommendations this paragraph gives some device specific recommendations to improve emc/emi performance. further generic design recommendations can be e.g. found on the freescale web site www.freescale.com. vsup terminals (vsup[1:8]) its recommended to place a high quality ceramic decoupling capacitor close to the vsup terminals to improve emc/emi behavior. lin terminal for dpi (direct power injection) and esd (electrostatic discharge) its recommended to place a high quality ceramic decoupling capacitor near the lin terminal. an additional varistor will further increase the immunity against esd. a ferrite in the lin line will suppress some of the noise induced. voltage regulator output terminals (vdd and vss) use a high quality ceramic decoupling capacitor to stabilize the regulated voltage. mcu digital supply te rminals (evdd and evss) fast signal transitions on mcu terminals place high, short- duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu. it is recommended that a high quality ceramic decoupling capacitor be placed between these terminals. mcu analog supply terminals (vrefh/vdda and vrefl/ vssa) to avoid noise on the analog supply terminals, its important to take special care on the layout. the mcu digital and analog supplies should be tied to the same potential via separate traces and connected to the voltage regulator output. figure 34 and figure 35 show the recommendations on schematics and layout level and table 23 indicates recommended external components and layout considerations. figure 34. emc/emi recommendations MM908E622 evdd vdd evss vss vsup[1:8] gnd[1:4] v sup + vdda/vrefh vssa/vrefl lin lin c1 c2 d1 c3 c4 c5 l1 v1
analog integrated circuit device data 58 freescale semiconductor 908e622 typical applications figure 35. pcb layout recommendations . 1 2 4 3 5 6 7 8 9 11 10 12 13 14 15 16 18 17 19 20 21 22 23 25 24 26 27 54 53 51 52 50 49 48 47 46 44 45 43 42 41 40 39 37 38 36 35 34 33 32 30 31 29 28 908e622 d1 lin vbat gnd3 gnd4 vsup3 vsup4 vsup5 vsup6 c3 c4 gnd v1 c5 c1 c2 l1 evdd evss vdda/vrefh vssa/vrefl vdd gnd1 vss vsup1 lin gnd2 vsup2 vsup7 vsup8 table 23. component value recommendation component recommended value (1) comments / signal routing d1 reverse battery protection c1 bulk capacitor c2 100nf, smd ceramic, low esr close to vsup terminals with good ground return c3 100nf, smd ceramic, low esr close (<3mm) to di gital supply terminals (evdd, evss) with good ground return. the positive analog (vrefh/ vdda) and the digital (evdd) supply should be connected right at the c3. c4 4,7uf, smd ceramic, low esr bulk capacitor c5 180pf, smd ceramic, low esr close (<5mm) to lin terminal. total capacitance on lin has to be below 220pf. (c total = c lin-terminal + c5 + c varistor ~ 10pf + 180pf + 15pf) v1 (2) varistor type tdk avr-m1608c270mbaab op tional (close to lin connector) l1 (2) smd ferrite bead type tdk mmz2012y202b optional, (close to lin connector) notes 1. freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit dr awings or tables. while freescale offers component recommendations in this configuration, it is the customer?s responsibility to valid ate their application. 2. components are recommended to improve emc and esd performance.
analog integrated circuit device data freescale semiconductor 59 908e622 package dimensions package dimensions important for the most current revision of the package, visit www.freescale.com and do a keyword search on the 98a drawing number: 98arl10519d. dwb suffix 54-terminal soicw-ep 98arl10519d issue a
analog integrated circuit device data 60 freescale semiconductor 908e622 additional information thermal addendum additional information thermal addendum integrated quad h-bridge, triple high-side and ec glass driver with embedded mcu and lin for mirror thermal addendum introduction this thermal addendum ia provided as a supplement to the MM908E622 technical data sheet. the addendum provides thermal performance information that may be critical in the design and devel opment of system a pplications. all electrical, application and packaging information is provided in the data sheet. package and thermal considerations this MM908E622 is a dual die package. there are two heat sources in the package independently heating with p 1 and p 2 . this results in two junction temperatures, t j1 and t j2 , and a thermal resistance matrix with r ja mn . for m , n =1, r ja11 is the thermal resistance from junction 1 to the reference temperature while only heat so urce 1 is heating with p 1 . for m =1, n =2, r ja12 is the thermal resistance from junction 1 to the reference temperature while heat source 2 is heating with p 2 . this applies to r j21 and r j22 , respectively. the stated values are solely for a thermal performance comparison of one package to another in a standardized environment. this methodology is not meant to and will not predict the perfor mance of a package in an application- specific environment. stated values were obtained by measurement and simulation according to the standards listed below. 54-terminal soicw-ep 908e622 dwb suffix 98arl105910 54-terminal soicw-ep note for package dimensions, refer to the 908e622 device datasheet. t j1 t j2 = r ja11 r ja21 r ja12 r ja22 . p 1 p 2 standards figure 36. thermal land pattern for direct thermal attachment per jedec jesd51-5 table 24. thermal pe rformance comparison thermal resistance 1 = power chip, 2 = logic chip [ c/w] m =1, n =1 m =1, n =2 m =2, n =1 m =2, n =2 r ja mn (1)(2) 23 20 24 r jb mn (2)(3) 9.0 6.0 10 r ja mn (1)(4) 52 47 52 r jc mn (5) 1.0 0 2.0 notes: 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-7and jesd51-5. 3. per jedec jesd51-8, with the board temperature on the center trace near the power outputs. 4. single layer thermal test board per jedec jesd51-3 and jesd51-5. 5. thermal resistance between the die junction and the exposed pad, ?infinite? heat sink attached to exposed pad. 1.0 1.0 0.2 0.2 soldermast openings thermal vias connected to t op buried plane 54 terminal soic-ep 0.65 mm pitch 17.9 mm x 7.5 mm body 10.3 mm x 5.1 mm exposed pad * all measurements are in millimeters
analog integrated circuit device data freescale semiconductor 61 908e622 additional information thermal addendum figure 37. thermal test board device on thermal test board r ja is the thermal resistance between die junction and ambient air. r jsmn is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package. this device is a dual die package. index m indicates the die that is heated. index n refers to the number of the die where the ju nction temperature is sensed. pta0/kbd0 pta1/kbd1 pta2/kbd2 pta3/kbd3 pta4/kbd4 vdda/vrefh evdd evss vssa/vrefl (pte1/rxd <- rxd) vss vdd hvdd l0 h0 hs3 vsup8 hs2 vsup7 hs1b hs1a vsup6 vsup5 gnd4 hb1 vsup4 flsvpp ptc4/osc1 ptc3/osc2 ptc2/mclk ptb5/ad5 ptb4/ad4 ptb3/ad3 irq rst (ptd0/tach0/bemf -> pwm) ptd1/tach1 rst_a irq_a lin a0cst a0 gnd1 hb4 vsup1 gnd2 hb3 vsup2 ec ecr testmode gnd3 hb2 vsup3 1 11 12 13 14 15 16 17 18 19 20 9 10 21 22 23 24 25 26 27 6 7 8 4 5 2 3 54 44 43 42 41 40 39 38 37 36 35 46 45 34 33 32 31 30 29 28 49 48 47 51 50 53 52 exposed pad 908e622 terminal connections 54-terminal soicw-ep 0.65 mm pitch 17.9 mm x 7.5 mm body a 10.3 mm x 5.1 mm exposed pad a material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a : cu heat-spreading areas on board surface ambient conditions: natural convection, still air table 25. thermal resistance performance thermal resistance area a (mm 2 ) 1 = power chip, 2 = logic chip ( c/w) m =1, n =1 m =1, n =2 m =2, n =1 m =2, n =2 r ja mn 053 48 53 300 39 34 38 600 35 30 34 r js mn 021 16 20 300 15 11 15 600 14 9.0 13
analog integrated circuit device data 62 freescale semiconductor 908e622 additional information thermal addendum figure 38. device on thermal test board r ja figure 39. transient thermal resistance r ja (1.0 w step response) device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 heat spreading area a [m m 2] thermal resistance [oc/w] 0 300 600 r ja11 r ja22 r ja12 =r ja21 x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time[s] thermal resistance [oc/w] r ja11 r ja22 r ja12 =r ja21 x
MM908E622 rev 1.0 09/2005 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should a buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, the buyer shall i ndemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

▲Up To Search▲

Price & Availability of MM908E622

	To Download MM908E622 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .